FinFET Gate Line Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As integrated circuit devices are downscaled, they face challenges in maintaining operation accuracy and speed while reducing undesired parasitic capacitance, which affects reliability due to the increased density of conductive regions.
Innovation Solution
The design incorporates a fin-type active region with a gate line featuring a connection protrusion portion and a recess top surface at different vertical levels, reducing parasitic capacitance by optimizing the area occupied by conductive regions and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of conductive regions is decreased to reduce parasitic capacitance, then reliability is improved, but the operation speed and accuracy may be affected due to down-scaling
Solution Approach 1:
The gate line is designed with a multi-level three-dimensional structure including a connection protrusion portion at a first vertical level and a main gate portion at a second vertical level. This vertical dimensionality change allows the gate line to occupy less horizontal area, reducing parasitic capacitance while maintaining effective gate control for transistor operation.
Solution Approach 2:
The gate line is segmented into distinct portions: a connection protrusion portion for electrical connection and a main gate portion for transistor control. This segmentation allows each portion to be optimized independently, with the connection portion providing reliable electrical contact and the main gate portion providing effective channel control with reduced parasitic capacitance.
2Reliability
If the area of conductive regions is decreased to reduce parasitic capacitance, then reliability is improved, but manufacturing complexity increases due to multi-level structure
Solution Approach 1:
The connection protrusion portion and main gate portion are merged into a single continuous gate line structure formed from the same conductive material layer. This merging approach reduces manufacturing complexity by eliminating the need for separate fabrication processes for different gate portions, while still achieving the desired multi-level configuration that reduces parasitic capacitance.
3Reliability
If the gate line area is reduced to decrease parasitic capacitance, then reliability is improved, but the gate control effectiveness may be compromised
Solution Approach 1:
The gate line utilizes vertical dimensionality with the connection protrusion portion extending to a first vertical level and the main gate portion at a second vertical level. This three-dimensional configuration reduces the horizontal footprint and parasitic capacitance while maintaining sufficient gate control effectiveness through the vertical positioning of the gate over the channel region.
Data Source
AI summary
An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.