FinFET Gate Mask Planarization for Pattern Loading Uniformity
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, pattern loading issues during the formation of FinFETs lead to material layers of varying heights, causing challenges in planarization and integration density, which affect the uniformity and performance of the devices.
Innovation Solution
A multi-step planarization process involving chemical mechanical polish (CMP) and non-selective etch-back is employed to level gate masks and interlayer dielectric masks, ensuring even heights and reducing pattern loading effects, allowing for the formation of FinFETs with channel regions of varying lengths and improved threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but pattern loading issues cause material layers to have varying heights
Solution Approach 1:
The planarization process is divided into multiple sequential steps: first CMP to level high regions, then etch-back to address remaining variations. This segmentation of the planarization function allows each step to target specific height variation causes, improving overall height uniformity despite continued feature size reduction
Solution Approach 2:
The first CMP process is performed preliminarily to remove excess material and level high regions before subsequent etch-back. This preliminary planarization prevents pattern loading from causing excessive height variations in later processing steps, enabling continued scaling while maintaining manufacturing precision
2Manufacturing precision
If multi-step planarization process is used to level material layers, then height uniformity is improved, but process complexity increases
Solution Approach 1:
The first CMP process acts as an intermediary step between material deposition and final device formation. It mediates the height variations caused by pattern loading by selectively removing material from high regions, creating a more uniform surface that reduces the burden on subsequent etch-back processes
Solution Approach 2:
The process transitions from a single planarization step to multiple steps with different parameters: first CMP uses mechanical polishing with specific pressure and slurry, then etch-back uses chemical etching with controlled selectivity. This parameter diversification allows each step to address different aspects of height variation efficiently
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively addresses pattern loading and planarity issues, enhancing the integration density and performance of FinFETs by maintaining uniformity across different channel lengths and reducing the risk of over/under etching during subsequent processing steps.
Implementation Method 1
depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process
Implementation Method 2
planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate
Data Source
AI summary
In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.