FinFET Gate Notch Alignment for Contact Shorting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In CMOS fabrication, the shrinking technology nodes pose challenges such as source/drain regions shorting to metal gate structures due to misalignment of contacts, exacerbated by decreasing gate length and spacing, which affects the performance of FinFET devices.
Innovation Solution
The implementation of a FinFET device with a gate last process using high-dielectric-constant gate dielectric layers and metal gate electrodes, along with specific etching and capping layer techniques to improve alignment and reduce short circuits, is proposed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length and spacing between devices are decreased to improve device density, then productivity increases, but manufacturing precision deteriorates due to misalignment of contacts with metal gate structures
Solution Approach 1:
The patent applies preliminary action by forming the metal gate structure before forming the source/drain regions and contacts. This sequence allows the metal gate to serve as a reference structure that defines the precise location where contacts will be formed, ensuring proper alignment even as dimensions shrink. The gate-last process modifies the traditional sequence to achieve this preliminary positioning effect.
Solution Approach 2:
The patent introduces an intermediary approach by using the metal gate structure itself as a positioning reference for contact formation. Rather than relying on separate alignment markers or complex multi-step alignment processes, the metal gate serves as the intermediary reference that directly guides contact placement, simplifying the alignment process at scaled dimensions.
2Reliability
If high-dielectric-constant gate dielectric layers are used to reduce gate leakage, then reliability improves, but device complexity increases due to additional processing steps
Solution Approach 1:
The patent merges the formation of the metal gate structure with the formation of the gate dielectric layer into a single integrated process sequence. Rather than forming the dielectric, then the gate, then additional alignment structures, the metal gate and dielectric are formed together in the gate-last process, reducing the total number of processing steps while maintaining the reliability benefits of high-k dielectric materials.
Data Source
AI summary
A semiconductor device includes a first fin, a first gate electrode, a second fin, a second gate electrode, and a first dielectric capping layer. The first fin extends along a direction. The first gate electrode is across the first fin and has a first notched corner. The second fin extends along the direction. The second gate electrode is across the second fin and has a second notched corner. The first dielectric capping layer has a first portion in between the first notched corner and the second notched corner.