FinFET Gate Notch Profile Control to Prevent Gate-Source Shorts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the manufacturing of FinFET devices, the traditional etching process for forming gate structures often results in different etching rates between the center and peripheral areas of a substrate, leading to uneven gate profiles and potential short circuits between the gate and source/drain areas.
Innovation Solution
The method involves applying a different flow rate of etching gas at the center and peripheral areas during dry plasma etching, and adjusting other etching parameters such as pressure, RF bias voltage, and over etching time, to ensure that both areas have two notch features with the same profile, thereby preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching process is used for forming gate structures, then manufacturing process is simple, but etching rates differ between center and peripheral areas causing uneven gate profiles
Solution Approach 1:
The patent applies local quality by differentiating etching parameters between center and peripheral areas of the substrate. Specifically, the etching gas flow rate is adjusted locally (higher at center, lower at periphery) to compensate for the natural variation in etching rates, ensuring uniform gate profiles across the entire substrate while maintaining a controlled etching process
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting multiple etching parameters including gas flow rate, pressure, RF bias voltage, and temperature across different spatial zones of the substrate. These parameter modifications enable precise control over etching rates in center versus peripheral areas, resolving the uniformity issue without excessive process complexity
2Reliability
If uniform etching is applied across the substrate, then process control is simple, but short circuits occur between gate and source/drain areas due to uneven profiles
Solution Approach 1:
The patent uses local quality by implementing spatially differentiated etching conditions to prevent short circuits. By applying higher etching gas flow rates and adjusted parameters specifically in the center area compared to the periphery, the process ensures uniform gate profiles that maintain proper spacing from source/drain regions, preventing short circuits while managing process control complexity
Solution Approach 2:
The patent incorporates feedback mechanisms through real-time monitoring of etching parameters and profile measurements. This feedback enables dynamic adjustment of gas flow rates, pressure, and RF bias voltage during the etching process to maintain uniform profiles and prevent short circuits, balancing reliability improvement with controlled process complexity
3Manufacturing precision
If different etching parameters are applied to center and periphery areas, then gate profile uniformity is improved, but process complexity increases
Solution Approach 1:
The patent applies local quality by implementing spatially differentiated etching parameters including gas flow rate, pressure, and RF bias voltage for center and periphery areas. This approach achieves uniform gate profiles across the substrate while managing manufacturing complexity through systematic parameter differentiation rather than overly complex process steps
Solution Approach 2:
The patent employs dynamics by making etching parameters adjustable and variable during the process. Gas flow rates, pressure, and RF bias voltage are dynamically modified based on spatial location and real-time process conditions, enabling precise control over etching uniformity while maintaining reasonable ease of manufacture through automated parameter adjustment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity of gate structures across the substrate, reduces the risk of short circuits, and enhances the electrical properties and stability of the FinFET devices, as validated by wafer acceptance tests.
Implementation Method 1
etching the gate layer by plasma etching with an etching gas to form a gate
Implementation Method 2
The etching gas during the plasma etching is supplied at a ratio of a flow rate at the center area to a flow rate at the periphery area
Data Source
AI summary
A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.