FinFET Gate Notch Profile Control Across Wafer Etch Regions
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Solution Overview
Problem
In the manufacturing of FinFET devices, the traditional etching process for forming gate structures often results in different etching rates between the center and periphery areas of the substrate, leading to uneven gate profiles and potential short circuits between the gate and source/drain areas.
Innovation Solution
The method involves applying a different flow rate of etching gas at the center area compared to the periphery area during dry plasma etching, and adjusting other etching parameters such as pressure, RF bias voltage, and over etching time to ensure that both the center and periphery gate structures have two notch features with the same profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching process is used for forming gate structures, then manufacturing process is simple, but etching rates differ between center and periphery areas leading to uneven gate profiles
Solution Approach 1:
The patent applies different etching gas flow rates to different regions (center vs. periphery) of the substrate during the etching process. This local differentiation ensures that each region receives the appropriate etching conditions to achieve uniform gate profiles across the entire substrate, directly resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent modifies etching process parameters (gas flow rate, pressure, RF bias voltage, over etching time) to optimize the etching rates in different substrate regions. By dynamically adjusting these parameters, the process achieves consistent gate profile uniformity while managing the complexity through systematic parameter control.
2Reliability
If uniform etching is applied across the substrate, then process control is simple, but gate structures in periphery area may have footing features causing short circuits
Solution Approach 1:
The patent implements region-specific etching conditions where the periphery area receives different gas flow rates compared to the center area. This local quality approach prevents footing features in the periphery that would cause short circuits, thereby improving reliability while accepting increased process control complexity.
Solution Approach 2:
The patent applies preliminary counter-actions by adjusting etching parameters before the actual etching occurs, specifically by modifying gas flow rates and other parameters in advance to prevent footing feature formation in periphery areas, thus preventing short circuits before they can occur.
3Manufacturing precision
If etching gas flow rate is increased at periphery area, then gate profile uniformity improves, but process parameters become more complex to manage
Solution Approach 1:
The patent applies different gas flow rates to different substrate regions, with the periphery area receiving optimized flow rates to achieve uniform gate profiles. This local quality approach directly improves manufacturing precision while the complexity is managed through systematic implementation of the differential flow rate strategy.
Solution Approach 2:
The patent systematically changes process parameters (gas flow rate, pressure, RF bias voltage, over etching time) to achieve the desired gate profile uniformity. By making these parameter changes in a controlled and systematic manner, the patent improves precision while keeping parameter management complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity of gate structures across the substrate, preventing short circuits and enhancing the electrical properties and stability of the FinFET devices, as verified by wafer acceptance tests.
Implementation Method 1
etching the gate material layer with an etching gas to a first depth to form a gate structure having a notch feature in a portion overlapped with sidewalls of the fin
Implementation Method 2
applying a different flow rate of etching gas at the center area compared to the periphery area during dry plasma etching
Data Source
AI summary
A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.