FinFET Gate Oxide Formation for Peripheral Leakage Control
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Solution Overview
Problem
In semiconductor fabrication, the reduction in feature size of integrated circuits leads to short-channel effects in traditional planar MOSFETs, where the gate electrode struggles to control the channel, resulting in subthreshold leakage. This is mitigated in Fin-FETs, but existing semiconductor structures still require improved electrical performance, particularly in peripheral devices with higher operation power voltage.
Innovation Solution
A method and structure for fabricating semiconductor devices involving the formation of fin structures in both peripheral and core regions, with specific gate and dielectric layer formations to enhance control and reduce leakage, including the creation of dummy gate structures, removal of dummy gate electrodes, and deposition of gate oxide and metal layers to form gate structures that improve gate-to-channel control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to accommodate smaller feature sizes, then the integration density increases, but the gate electrode loses sufficient control over the channel resulting in subthreshold leakage
Solution Approach 1:
The patent transitions from planar MOSFETs to Fin-FET architecture, moving the channel structure from a two-dimensional planar configuration to a three-dimensional vertical fin structure. This dimensional change allows the gate to control the channel from multiple surfaces (top and sidewalls), significantly improving gate control ability while maintaining reduced channel length for high integration density
2Reliability
If the gate dielectric layer thickness is increased in peripheral devices to prevent electrical breakdown, then the device reliability improves, but the device complexity increases due to different thickness requirements for core and peripheral devices
Solution Approach 1:
The patent implements different gate dielectric layer thicknesses in different regions: a first gate dielectric layer thickness in peripheral devices and a second gate dielectric layer thickness in core devices. This local differentiation allows each region to have optimized dielectric thickness according to its specific electrical requirements, improving reliability while managing complexity through regional specialization
Solution Approach 2:
The substrate is divided into distinct core region and peripheral region, with separate gate dielectric layer configurations for each. This segmentation allows independent optimization of dielectric thickness in each region, addressing the different electrical requirements of core and peripheral devices
Data Source
AI summary
A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a peripheral region of a substrate and a plurality of second fin structures in a core region of the substrate, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure together with each second dummy gate electrode layer, forming a first gate oxide layer on the exposed portion of each first fin structure, and then removing each second dummy gate oxide layer. The method further includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.