FinFET Gate Oxide Formation via ISSG and ALD
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Solution Overview
Problem
Current methods for forming gate oxide layers in fin field effect transistors (FinFETs) are ineffective, either consuming excessive silicon or resulting in large leakage currents.
Innovation Solution
A method integrating in-situ steam generation (ISSG) and atomic layer deposition (ALD) processes to form consecutive oxide layers on fin-shaped structures, which reduces silicon consumption and improves leakage current by forming a gate dielectric layer effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If conventional methods are used to form gate oxide layer in FinFETs, then the gate dielectric layer can be formed, but excessive silicon is consumed
Solution Approach 1:
The patent changes the oxidation parameters by performing a first oxidation at a first temperature to form a first oxide layer, then performing a second oxidation at a second temperature (different from the first) to form a second oxide layer. This temperature parameter change enables precise control over oxidation depth and rate, reducing unnecessary silicon consumption while maintaining gate oxide layer quality
Solution Approach 2:
The patent segments the gate oxide layer formation into two distinct oxidation steps: a first oxidation forming a first oxide layer with specific properties, and a second oxidation forming a second oxide layer with different properties. This segmentation allows each step to be optimized independently for minimal silicon consumption while ensuring reliable gate oxide formation
2Reliability
If conventional methods are used to form gate oxide layer in FinFETs, then the gate dielectric layer can be formed, but large leakage current is observed
Solution Approach 1:
The patent employs parameter changes by conducting oxidations at different temperatures to create oxide layers with different electrical properties. The first oxidation at the first temperature produces an oxide layer with specific leakage characteristics, while the second oxidation at the second temperature produces an oxide layer that complements it, together achieving low leakage current
Solution Approach 2:
The patent creates a composite gate dielectric structure consisting of a first oxide layer and a second oxide layer, each formed under different oxidation conditions. This composite structure combines the beneficial electrical properties of both layers to achieve low leakage current that neither layer could achieve alone
3Length of moving object
If the critical dimension of fin width is reduced, then transistor scaling is achieved, but manufacturing precision becomes more difficult
Solution Approach 1:
The patent uses parameter changes (different oxidation temperatures) to achieve precise control over oxide layer formation at reduced fin widths. The first oxidation at the first temperature and second oxidation at the second temperature allow independent control of oxidation depth and rate, maintaining manufacturing precision even as fin width decreases for scaling
Solution Approach 2:
The patent performs a preliminary first oxidation to form a first oxide layer that prepares the silicon surface for the subsequent second oxidation. This preliminary action creates a controlled interface that facilitates precise oxidation control in the second step, enabling accurate dimension control at scaled fin widths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces silicon consumption and minimizes leakage current, thereby shrinking the critical dimension of fin width and enhancing the performance of FinFET devices.
Implementation Method 1
forming a first oxide layer on the first fin-shaped structure
Implementation Method 2
forming a second oxide layer on the first oxide layer and the STI
Data Source
AI summary
A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.