FinFET Gate Oxide Liner for Thick Oxide With Low Silicon Loss
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Solution Overview
Problem
Existing FinFET devices face challenges in maintaining reasonable gate oxide thickness greater than 60 Å with high quality and minimal silicon loss, leading to increased parasitic capacitance and degraded short channel effects, particularly in high voltage applications like DRAM peripheral CMOS.
Innovation Solution
Formation of a relatively thick gate oxide for FinFETs using a dielectric liner and oxidation processes such as ISSG or RTO, combined with a protective nitride liner to constrain epitaxial processing, ensuring uniform composition and minimal silicon loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate oxide formation methods are used, then manufacturing simplicity is maintained, but gate oxide thickness cannot be increased beyond 60 Å without excessive silicon loss and quality degradation
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary between the silicon fin and the gate electrode. This sacrificial oxide serves as a template that defines the gate oxide thickness without requiring direct oxidation of the silicon fin, thereby preventing silicon loss while enabling precise control of gate oxide thickness up to 60 Å or greater
Solution Approach 2:
The sacrificial oxide layer is formed preliminarily before the gate electrode deposition. This preliminary formation establishes a predefined thickness reference that guides subsequent processing steps, ensuring that the final gate oxide structure achieves the desired thickness without excessive silicon consumption
2Reliability
If gate oxide thickness is increased for high voltage applications, then voltage handling capability is improved, but parasitic capacitance increases and short channel effects degrade
Solution Approach 1:
The gate oxide structure is designed with local quality variations: a thin interface oxide layer at the silicon-gate oxide interface to minimize parasitic capacitance and maintain good electrical contact, combined with a thicker bulk gate oxide layer to provide the necessary voltage handling capability. This layered approach with different thicknesses at different locations within the gate oxide structure resolves the contradiction between voltage handling and parasitic effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in high-quality thick gate oxides with reduced silicon loss, improving FinFET performance in high voltage components by enhancing gate control and reducing parasitic capacitance.
Implementation Method 1
an oxide liner on the fin from the substrate to a top of the fin, including on the top of the fin... the fin having a thickness of uniform composition defined by in situ steam generation or rapid thermal oxidation of the oxide
Implementation Method 2
a protective liner on a portion of the oxide liner... to constrain epitaxial processing
Data Source
AI summary
A variety of applications can include devices implementing one or more fin field-effect transistors (FinFETs) with gate oxide thickness that address thicker gate oxide quality with minimum material loss in the fins of the FinFETs for high voltage devices. The gate oxides can be fabricated with thicker oxides than gate oxides of FinFETs used with capacitors in memory cells of memory arrays. These gate oxides can be formed as oxide liners by oxidation with use of a protective liner to maintain uniform composition of material for the fin during FinFET processing.