FinFET Gate Oxide Thickness Variation via Selective Masking

The substrate is divided into different regions (first region and second region) with different gate oxide thickness requirements. Each region is processed independently using selective masking, allowing different gate oxide thicknesses to be formed without requiring multiple complete process iterations that would introduce contamination.

Different gate oxide thicknesses are formed in different local regions of the substrate. A mask is applied selectively to the second region to protect it during etching, while the first region receives the full etch to create thinner gate oxide. This local differentiation achieves versatility without compromising overall reliability.

Multiple gate oxide thickness formation operations are merged into a single etch process by using selective masking. Instead of performing separate oxidize-mask-etch iterations for each thickness requirement, the patent combines these operations into one process step where different regions receive different treatments simultaneously, reducing manufacturing complexity and cost.

A mask is applied in advance to the second region before the etch process to protect it from forming thin gate oxide. This preliminary masking action allows the subsequent single etch process to create both thin and thick gate oxide regions as intended, eliminating the need for multiple process iterations and reducing manufacturing cost.

A mask serves as an intermediary protective layer during the etch process. The mask prevents etchants from attacking the gate oxide in regions where thick gate oxide is desired, while allowing the etch to proceed in regions where thin gate oxide is intended. This intermediary protection maintains gate oxide thickness precision while still enabling gate terminal formation.

The mask is applied beforehand to counteract the harmful effect of the etch process on the gate oxide. By preventing the etchant from contacting the gate oxide in protected regions before the etch occurs, the mask eliminates the compromise to gate oxide thickness that would otherwise result from the necessary etching of dummy gates.

Different gate oxide thicknesses are assigned to different functional regions of the device. High voltage devices receive thick gate oxide for reliability, while logic devices receive thin gate oxide for high speed performance. This local quality differentiation allows each device type to operate at its optimal performance point without compromising the other.

The device structure is segmented into different functional regions with different gate oxide thickness requirements. By dividing the substrate into regions suitable for different device types and applying selective etching and masking, the patent enables co-existence of high-voltage reliable devices and high-speed logic devices on the same substrate.