FinFET Gate Stack Passivation for Low-Temperature Defect Repair
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as defects in gate dielectric layers that affect device performance, including dangling bonds and oxygen vacancies, which existing technologies struggle to address effectively without damaging the transistor.
Innovation Solution
A passivation treatment using a remote plasma process introduces fluorine or nitrogen radicals into the gate dielectric layers, facilitated by an n-type work function metal, to fix defects and improve conformity, performed at a low temperature to minimize damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional defect treatment methods are used on gate dielectric layers, then defects may be addressed, but the transistor is damaged
Solution Approach 1:
The patent changes the temperature parameter to below 100°C and modifies the plasma process parameters to create a low-energy environment. This allows defect treatment to proceed without providing enough thermal energy or particle energy to cause transistor damage, thus resolving the contradiction between effective defect treatment and preventing device damage
Solution Approach 2:
The patent replaces conventional thermal or high-energy defect treatment methods with a low-temperature plasma process. This substitution uses chemically active species at low temperatures instead of high thermal energy, enabling defect passivation without the mechanical/thermal stress that would damage the transistor structure
2Reliability
If high temperature processing is used to treat defects, then defect reduction may be achieved, but thermal damage occurs to the transistor
Solution Approach 1:
The patent fundamentally changes the temperature parameter from conventional high-temperature processing to below 100°C. This parameter change enables defect treatment through chemical means rather than thermal activation, achieving defect reduction while maintaining an extremely low thermal budget that prevents thermal damage to the transistor
3Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but defects in gate dielectric layers increase
Solution Approach 1:
The patent changes the deposition temperature parameter to below 100°C during gate dielectric formation. This parameter change reduces thermal stress and prevents defect formation during the deposition process itself, maintaining high gate dielectric quality even as feature sizes are reduced to increase integration density
Solution Approach 2:
The patent replaces thermal processing with low-temperature plasma processing for gate dielectric formation and defect treatment. This substitution eliminates thermal damage mechanisms that become more problematic at smaller feature sizes, preserving gate dielectric quality while enabling continued scaling for higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces defects in gate dielectric layers, enhancing device performance and reliability while maintaining a low thermal budget to prevent transistor damage.
Implementation Method 1
A passivation treatment using a remote plasma process introduces fluorine or nitrogen radicals into the gate dielectric layers
Implementation Method 2
introduces fluorine or nitrogen radicals into the gate dielectric layers, facilitated by an n-type work function metal, to fix defects
Data Source
AI summary
A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.