FinFET Gate Patterning via Double Patterning Memorization
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Solution Overview
Problem
Existing FinFET fabrication techniques, such as Litho-Freeze-Litho-Etch (LFLE), face challenges with non-uniform gate length control, high line edge roughness, and etch bias due to the use of immiscible resists, leading to inconsistent and unreliable results.
Innovation Solution
The implementation of a double patterning memorization technique using a front end of the line (FEOL) Lithography-Etch, Lithography-Etch (LELE) process, which employs identical resist materials for both patterning steps and a single hardmask, resulting in improved critical dimension uniformity and reduced line edge roughness, and enables a more reliable gate pattern transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the Litho-Freeze-Litho-Etch (LFLE) process is used to form FinFET gates, then double patterning can be achieved to enable scaling below single patterning limits, but gate length control becomes non-uniform and line edge roughness increases due to the use of immiscible resists
Solution Approach 1:
The patent applies homogeneity by using the same resist material for both lithography steps in the double patterning process, eliminating the non-uniformity caused by immiscible resists. This ensures consistent etch resistance and chemical freeze response across all patterns, resulting in uniform gate length control and reduced line edge roughness.
Solution Approach 2:
The patent changes the key parameter of resist material identity from variable (different resists for each step) to constant (same resist for both steps). This parameter change fundamentally resolves the non-uniformity issues while maintaining the ability to achieve double patterning for scaled device dimensions.
2Ease of manufacture
If the chemical freeze process is used in the LFLE method, then pattern transfer can be achieved, but defects and performance issues consistently occur
Solution Approach 1:
By using identical resist materials for both patterning steps, the patent ensures uniform chemical freeze response across all structures. This homogeneity eliminates the performance variability and defect formation that occur when different resist types respond differently to the chemical freeze process.
3Adaptability or versatility
If two different immiscible resists are used in the LFLE process, then succeeding lithography steps can be enabled, but etch bias increases due to different etch resistance of the resists
Solution Approach 1:
The patent uses the same resist material for both lithography steps, ensuring uniform etch resistance across all patterns. This eliminates the etch bias that occurs when different resist types have different etch resistance properties, resulting in more precise pattern transfer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides consistent and reliable gate patterning with improved uniformity and reduced defects, addressing the limitations of the LFLE method by ensuring uniform CDU and LER/LWR values and minimizing etch bias, thereby enhancing the reliability of FinFET device fabrication.
Implementation Method 1
performing a lithography-etch, lithography-etch process to form a set of trenches
Implementation Method 2
performing a lithography-etch, lithography-etch process to form a set of trenches
Implementation Method 3
polishing the oxide layer
Data Source
AI summary
Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.