FinFET Gate Patterning via Shallow Trench Isolation
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Solution Overview
Problem
The manufacturing of FinFET devices faces challenges such as increased difficulty in defining device features as feature sizes shrink, topography-dependent processing inefficiencies, and the need for integration of different channel materials, particularly due to aggressive etching processes and elevated temperature requirements.
Innovation Solution
A method involving shallow trench isolation structures to conceal fin sidewalls, postponing the 3D formation of fin structures, and using epitaxial growth to replace upper portions with different semiconductor materials, allowing for more controlled and efficient processing steps and integration of various channel materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fins are formed before gate patterning with conventional methods, then device features can be defined, but thin fins are damaged by aggressive etching processes and large topography is introduced
Solution Approach 1:
The patent forms a dummy gate structure before patterning the fins. This preliminary gate structure serves as a protective element during subsequent etching processes, preventing damage to thin fins while enabling precise feature definition through controlled material removal around the dummy gate.
Solution Approach 2:
The dummy gate acts as an intermediary structure that mediates between the fin formation and final gate patterning steps. It protects the fins during processing while allowing precise definition of device features, and is later removed to reveal the properly defined fin structures.
2Reliability
If 3D FinFET structures are manufactured with conventional topography-dependent processes, then device functionality is achieved, but processing efficiency deteriorates due to increased topography
Solution Approach 1:
The patent performs gate patterning and fin definition steps before the fins become tall 3D structures. By completing critical patterning operations while the structure remains relatively flat, processing efficiency is maintained while still achieving the desired 3D FinFET functionality in subsequent steps.
Solution Approach 2:
Instead of forming tall fins first and then patterning gates (conventional approach), the patent inverts the sequence by establishing the gate pattern first, then forming fins that grow around and between the gate structures. This inversion allows processing to occur on a flatter surface, improving efficiency.
3Reliability
If elevated temperature processing is used for source/drain anneal, then material properties are improved, but material selection is limited
Solution Approach 1:
The patent performs source/drain annealing at elevated temperatures before depositing sensitive channel materials. By completing thermal processing steps first, the substrate and underlying structures are pre-conditioned, allowing subsequent deposition of temperature-sensitive materials without degradation, thus expanding material selection versatility.
4Reliability
If conventional gate-first or gate-last approaches are used, then FinFET devices can be manufactured, but integration of different channel materials becomes complex or impossible
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: first forming the gate and fin structures, then separately introducing different channel materials into specific regions. This segmentation allows different materials (e.g., Si, Ge, III-V) to be integrated into different fins or channel regions independently, enabling multi-material FinFET devices.
Solution Approach 2:
The patent enables different channel materials to be deposited in different local regions of the device. By controlling material deposition to specific fin or channel regions after the gate structure is formed, each region can have optimized material properties tailored to its specific functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances processing efficiency by maintaining a flat topography, preserving abrupt fin angles, and enabling the use of materials that would otherwise be unusable, thus improving reproducibility and device characteristics while allowing for larger fin heights and varied channel materials.
Implementation Method 1
the sidewalls of the fin structures are fully concealed (e.g., covered) by the shallow trench isolation structures
Implementation Method 2
using epitaxial growth to replace upper portions with different semiconductor materials
Data Source
AI summary
A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.