FinFET Gate Pitch and S/D Depth Integration for Logic and SRAM
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Solution Overview
Problem
Existing semiconductor manufacturing processes struggle to efficiently integrate multi-gate transistors with different constructions to meet varying design needs, such as high speed, high circuit density, and low leakage, while maintaining similar processes and process windows to reduce costs and improve yield.
Innovation Solution
The integration of FinFET devices with varying gate pitches and source/drain depths in different circuit regions, allowing for the fabrication of transistors with distinct design requirements, such as high-speed logic circuits and high-density memory regions, by adjusting the gate lengths, spacings, and source/drain depths to optimize performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-gate transistors with different constructions are integrated to meet varying design needs (high speed, high density, low leakage), then device performance and adaptability are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent applies local quality by implementing different FinFET constructions in different regions of the semiconductor device. First FinFETs with a first gate pitch are used in logic circuit regions requiring high speed, while second FinFETs with a second gate pitch are used in memory circuit regions requiring high density. This allows each region to have optimized transistor characteristics tailored to its specific functional requirements.
Solution Approach 2:
The patent segments the semiconductor device into different circuit regions with distinct transistor constructions. The device is divided into logic circuit regions and memory circuit regions, each employing FinFETs with different gate pitches. This segmentation enables independent optimization of each region's performance characteristics while maintaining overall device functionality.
2Productivity
If different gate pitches and source/drain depths are used for different transistor types, then performance optimization is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming mandrels with different pitch values before creating the FinFET structures. The first mandrels are formed with a first pitch value and the second mandrels with a second pitch value, establishing the dimensional framework early in the manufacturing process. This preliminary structuring guides subsequent deposition and etching steps to achieve the required different gate pitches and source/drain depths with controlled precision.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying gate pitch and source/drain depth parameters across different transistor types. First FinFETs use a first gate pitch optimized for logic circuits, while second FinFETs use a second gate pitch optimized for memory circuits. The source/drain depths are also adjusted accordingly, allowing performance optimization through controlled parameter variation rather than requiring entirely different manufacturing processes.
3Ease of manufacture
If multiple transistor constructions are fabricated using similar processes, then manufacturing cost is reduced, but process window control becomes more difficult
Solution Approach 1:
The patent applies universality by using a common FinFET fabrication process framework that can accommodate multiple transistor constructions. The same basic process steps (mandrel formation, gate dielectric deposition, gate electrode formation, source/drain processing) are used for both first and second FinFETs, with only specific parameters (gate pitch, source/drain depth) varying. This universal approach maintains process similarity and reduces manufacturing complexity while enabling different transistor types.
Data Source
AI summary
A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first gate structure of a first gate pitch, a first channel region under the first gate electrode, a first source/drain (S/D) feature contacting the first channel region and having a first S/D depth. The second transistor includes a second gate structure of a first gate pitch, a second channel region under the first gate electrode, a second S/D feature contacting the second channel region and having a second S/D depth. The second gate pitch is larger than the first gate pitch. The second S/D depth is larger than the first S/D depth.