FinFET Gate Formation via Planarized Dielectric Etching
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Solution Overview
Problem
Conventional methods for forming FinFET devices face challenges in achieving uniform and reliable etching of dummy gate stacks and sidewall spacers due to their three-dimensional nature, leading to inconsistent fabrication results.
Innovation Solution
The process involves forming a dummy gate stack and sidewall spacers on a flat surface created by planarizing dielectric fill material, allowing for controlled and uniform anisotropic etching, and subsequently performing a replacement gate procedure to form a gate structure transversely overlying semiconductor fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods form dummy gate stacks and sidewall spacers on three-dimensional FinFET structures, then the gate structure can be formed, but uniform and reliable etching becomes difficult to achieve
Solution Approach 1:
The patent applies preliminary action by forming a planarized dielectric layer before creating the dummy gate stack and sidewall spacers. This pre-planarization step creates a flat foundation that enables uniform etching of the dummy gate and spacers, eliminating the three-dimensional etching difficulties that would otherwise occur on FinFET structures. The planar surface is prepared in advance to ensure consistent material deposition and removal in subsequent processing steps.
Solution Approach 2:
The patent introduces a planarized dielectric layer as an intermediary between the FinFET structure and the dummy gate stack formation. This intermediate layer serves as a flat platform that mediates the complex interaction between the three-dimensional fin structure and the planar fabrication processes. The dielectric layer absorbs the geometric complexity, allowing standard planar etching and deposition techniques to be applied uniformly.
2Manufacturing precision
If planarized dielectric fill material is used to create a flat surface, then uniform anisotropic etching of dummy gate stacks and sidewall spacers is achieved, but additional processing steps are required
Solution Approach 1:
The patent applies self-service through self-aligned processes where the planarized dielectric layer and subsequently formed structures serve as their own alignment references. The flat surface automatically provides a uniform baseline for dummy gate formation, and the dummy gate itself serves as the alignment reference for sidewall spacer deposition. This self-alignment eliminates the need for additional photolithography alignment steps, making the increased processing complexity self-justifying through improved precision.
3Manufacturing precision
If the dummy gate structure is removed and replacement gate procedure is performed, then accurate gate structure formation is achieved, but fabrication time increases
Solution Approach 1:
The replacement gate procedure applies preliminary action by forming the gate dielectric layer and performing precise etching operations on the planarized structure before final gate material deposition. This preliminary preparation on a flat surface ensures accurate gate alignment and dimensions are established early, preventing the need for corrective steps later. The initial precise formation on the planar surface reduces overall fabrication time compared to attempting corrections on three-dimensional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more reliable and consistent fabrication of FinFET devices by ensuring uniform etching and integration with existing process flows, improving the accuracy and reliability of the gate structure formation.
Implementation Method 1
depositing an insulating material overlying the semiconductor fin structure
Implementation Method 2
depositing an insulating material overlying the semiconductor fin structure
Implementation Method 3
creating a flat surface from the deposited insulating material
Implementation Method 4
forming spacers adjacent sidewalls of the dummy gate structure
Implementation Method 5
removing the dummy gate structure while leaving the spacers substantially intact
Implementation Method 6
selectively etching some of the deposited insulating material below an area defined between the spacers, and in a manner that is self-aligned with the spacers
Data Source
AI summary
A method of manufacturing a finned semiconductor device structure is provided. The method begins by providing a substrate having bulk semiconductor material. The method continues by forming a semiconductor fin structure from the bulk semiconductor material, depositing an insulating material overlying the semiconductor fin structure such that the insulating material fills space adjacent to the semiconductor fin structure, and planarizing the deposited insulating material and the semiconductor fin structure to create a flat surface. Thereafter, a replacement gate procedure is performed to form a gate structure transversely overlying the semiconductor fin structure.