FinFET Gate Plug Hard Mask Structure for Lower Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing contact resistance variations in field-effect transistors as they scale down, which affects the performance and efficiency of integrated circuits.
Innovation Solution
The manufacturing process involves forming a three-dimensional structure with fin-based field-effect transistors (FinFETs) using advanced techniques like double-patterning or multi-patterning processes, where gate structures with spacers and conductive layers are carefully aligned and etched to reduce contact resistance and enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but contact resistance variation increases
Solution Approach 1:
The patent applies local quality by forming a dedicated contact region with modified material properties (different composition or structure) within the semiconductor device. This localized structural modification targets specifically the contact area to reduce contact resistance variation without requiring changes to the overall device geometry or fabrication process, thereby maintaining high functional density while improving electrical contact reliability.
2Quantity of substance
If functional density is increased by scaling down, then more circuits fit on chip area, but contact resistance variation increases affecting performance
Solution Approach 1:
The invention introduces a contact region with distinct material or structural characteristics localized at the contact interface. This local modification addresses contact resistance issues directly without affecting the overall device scaling or functional density, allowing high device counts per chip area while maintaining reliable electrical contacts.
3Ease of manufacture
If existing field-effect transistor structures are used, then manufacturing is simpler, but contact resistance variation remains high
Solution Approach 1:
The patent implements preliminary action by forming the contact region with modified material properties during the standard fabrication sequence, integrating the contact optimization into the existing manufacturing flow. This approach reduces contact resistance variation without requiring separate additional processing steps or complex manufacturing procedures, maintaining ease of manufacture while improving electrical performance.
Data Source
AI summary
A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.