FinFET Sacrificial Gate Profile for Uniform Metal Gate Recess

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In advanced FinFET devices, achieving consistent metal gate structure recessing is challenging due to variations in metal structures and threshold voltages, which can lead to inadequate electrical separation between the metal gate electrode and adjacent contacts, and potential damage to the underlying fin structure during etching.

Innovation Solution

The profile of the sacrificial gate electrode is adjusted to have a narrow portion above the fin top area, allowing for controlled etching conditions to match the desired metal gate structure height, ensuring uniform etching rates and preventing damage to the fin structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching is used to recess the metal gate structure, then the metal gate electrode can be recessed, but the etching rate varies due to different metal structures leading to inconsistent recess depth and potential damage to the fin structure

Engineering Contradiction:
Improverecess depth consistencyVSAvoidfin structure integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A sacrificial gate electrode made of polysilicon is introduced as an intermediary structure during the gate replacement process. This sacrificial electrode serves as a template that defines the gate space, allowing for uniform etching of the metal gate structure. The polysilicon material provides consistent etching characteristics that enable precise control over the recess depth without damaging the underlying fin structure, thereby resolving the contradiction between manufacturing precision and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the metal gate structure is recessed to achieve electrical separation, then sufficient isolation can be obtained, but the etching process may damage the underlying fin structure

Engineering Contradiction:
Improveelectrical separationVSAvoidfin structure damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The sacrificial gate electrode is formed in advance as a protective template before the metal gate structure is recessed. This preliminary structure defines the etching boundaries and protects the underlying fin structure from damage during the etching process. The sacrificial electrode is removed after serving its protective function, leaving the desired electrical separation without fin structure damage.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If variations in metal structures are accommodated, then different threshold voltages can be achieved, but consistent recessing of the metal gate structure becomes difficult

Engineering Contradiction:
Improvethreshold voltage variationVSAvoidgate structure uniformity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The invention changes the material parameter of the gate electrode from direct metal deposition to a two-step process: first forming a polysilicon sacrificial electrode, then replacing it with metal. This parameter change in the fabrication process allows for consistent geometric definition through the polysilicon template while enabling subsequent variation in metal layer properties (such as work function through different metal materials or thickness) to achieve different threshold voltages, thus resolving the contradiction between adaptability and manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables precise control over the recessed metal gate structure height, improving device performance and yield by maintaining sufficient electrical separation and preventing damage to the channel region.

Implementation Method 1

the patterning the polysilicon layer comprises a plasm dry etching using HBr gas and Cl2 gas

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS11824103B2Method of manufacturing a semiconductor device and a semiconductor device
Publication Date: 2023.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11824103B2 patent drawing
  • US11824103B2 patent drawing
  • US11824103B2 patent drawing

AI summary

In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.