FinFET Gate Profile Optimization via ILD Stress Engineering
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Solution Overview
Problem
Existing FinFET devices and fabrication methods have limitations in achieving optimal performance and efficiency, particularly in reducing short channel effects and enhancing current flow, especially as the semiconductor industry advances into nanometer technology process nodes.
Innovation Solution
The method involves forming a FinFET device structure with a fin structure over a substrate, using a dielectric and mask layer patterning process, followed by etching and insulation, and then forming dummy gate structures with spacers and source/drain structures, where an ion implantation process is used to alter the stress properties of the inter-layer dielectric (ILD) structure, resulting in different trench widths for gate structures to optimize transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET fabrication methods are used, then basic device functionality is achieved, but saturation current and transistor performance are insufficient
Solution Approach 1:
The patent applies different stress conditions to different regions of the FinFET device. Specifically, compressive stress is applied to the channel region through the ILD structure to enhance hole mobility and saturation current, while tensile stress is applied to other regions to optimize electron mobility. This local differentiation of stress properties directly addresses the contradiction by improving transistor performance in critical regions without compromising overall device functionality.
Solution Approach 2:
The patent changes the physical and chemical parameters of the ILD structure through ion implantation doping. By modifying the dopant concentration and type in the ILD, the stress properties are altered to generate the desired compressive or tensile stress in the channel region. This parameter change enables enhanced saturation current while maintaining device reliability, resolving the technical contradiction.
2Ease of manufacture
If uniform gate structures are used, then fabrication simplicity is maintained, but optimal performance for both N-type and P-type transistors cannot be achieved
Solution Approach 1:
The patent implements different gate structure configurations for N-type and P-type transistor regions. The gate length, width, and stress conditions are locally optimized for each transistor type. This allows each transistor type to achieve optimal performance characteristics while using a relatively simple uniform fabrication process across the entire wafer, thus resolving the contradiction between fabrication simplicity and transistor performance.
Solution Approach 2:
The patent segments the device into distinct N-type and P-type transistor regions, each with optimized gate structures. By dividing the device into functional segments with different requirements, the patent achieves optimal performance for both transistor types while maintaining a systematic fabrication approach that doesn't significantly increase manufacturing complexity.
3Productivity
If short channel dimensions are used, then device density is increased, but short channel effects are enhanced
Solution Approach 1:
The patent uses stress applied through the ILD structure to counterbalance the detrimental effects of short channel dimensions. By introducing compressive stress in the channel region, the patent compensates for the loss of gate control that occurs with shorter channel lengths. This allows high device density to be achieved while maintaining reliable transistor operation and suppressing short channel effects.
Solution Approach 2:
The patent changes the stress parameter in the channel region through ion implantation doping of the ILD structure. This parameter change effectively extends the electrical length of the channel without physically increasing the dimensional length, thereby maintaining gate control and reducing short channel effects while preserving the benefits of high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of FinFET devices by adjusting the stress properties of the ILD structure, leading to increased saturation current and enhanced performance of both N-type and P-type transistors, with specific trench widths and angles optimizing the transistor characteristics.
Implementation Method 1
an ion implantation process is used to alter the stress properties of the inter-layer dielectric (ILD) structure
Data Source
AI summary
A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width.