FinFET Gate Profile Tuning for On-Current and Off-Current Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in achieving optimal electrical properties for integrated circuits, particularly in forming FinFET devices with precise gate structures that require different dopant profiles to enhance on-current and off-current performance.
Innovation Solution
The method involves forming semiconductor fins on a substrate, creating interlayer dielectrics, and using ion implantation to dope regions for forming dummy gate structures with varying profiles, followed by etching and patterning to achieve specific gate structures, and then replacing these with metal gate structures to improve electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used to form gate structures, then the manufacturing process is simple, but the electrical properties (on-current and off-current) are insufficient
Solution Approach 1:
The patent applies local quality by forming dummy gate structures with different profiles (first dummy gate structure with first profile, second dummy gate structure with second profile) in different local regions of the semiconductor device. This allows each region to have optimized electrical characteristics tailored to its specific functional requirements, thereby improving overall electrical properties without requiring complete redesign of the entire gate structure.
Solution Approach 2:
The gate structure is segmented into multiple distinct components: first dummy gate structures, second dummy gate structures, and metal gate structures. Each segment serves a specific purpose and can be independently optimized. The segmentation allows for different material compositions and geometric profiles in different segments, enabling precise control over electrical properties while maintaining manufacturing feasibility.
2Reliability
If dummy gate structures with varying profiles are formed, then electrical properties are enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs preliminary action by forming dummy gate structures before the final metal gate structures. These dummy structures serve as placeholders and templates that guide subsequent manufacturing steps. The first and second dummy gate structures are formed with specific profiles in advance, allowing the metal gate structures to be deposited and patterned more easily, thus reducing the complexity of the overall manufacturing process despite the varied final gate profiles.
Solution Approach 2:
The dummy gate structures act as intermediaries between the substrate and the final metal gate structures. They facilitate the manufacturing process by providing a temporary structure that can be formed with precise profiles using standard techniques, and then used as a template for the final gate structure formation. This intermediary approach simplifies the overall manufacturing complexity by breaking down the complex gate formation into manageable steps.
3Reliability
If metal gate structures are used, then electrical properties improve, but the device structure becomes more complex
Solution Approach 1:
The patent utilizes composite materials by combining different materials in the gate structures. The metal gate structures are formed with specific metal materials that provide superior electrical properties compared to conventional gates. The composite structure includes the metal gate material combined with the underlying semiconductor and insulator layers, creating a multi-material system that optimizes electrical performance while managing the increased structural complexity through systematic material selection and arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the enhancement of electrical properties such as on-current and off-current in FinFET devices by forming gate structures with distinct profiles, enabling better performance in integrated circuits.
Implementation Method 1
using ion implantation to dope regions for forming dummy gate structures
Data Source
AI summary
An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.