FinFET Gate Stack Protrusions Reduce Parasitic Capacitance
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Solution Overview
Problem
Existing FinFET devices and manufacturing methods are not entirely satisfactory in achieving optimal performance and complexity in IC manufacturing, particularly in scaling down processes.
Innovation Solution
A method for forming a FinFET device involving the formation of fins on a substrate, followed by the creation of a dummy gate stack using bromine and chlorine containing etching gases, and subsequent replacement with a gate stack to reduce parasitic capacitance and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET devices are scaled down to increase functional density, then production efficiency and cost are improved, but manufacturing complexity increases
Solution Approach 1:
The gate stack is segmented into multiple parts: a main gate portion and protruding parts extending beyond the fin width. This segmentation allows different regions of the gate to serve different functions - the main gate for primary control and the protruding parts for reducing parasitic capacitance, thereby improving device performance without increasing overall manufacturing complexity
Solution Approach 2:
The gate stack is designed with non-uniform structure where protruding parts are located specifically at regions adjacent to the source and drain regions. This local modification targets the specific area where parasitic capacitance occurs, reducing it without affecting other parts of the device and maintaining manufacturing simplicity
2Ease of manufacture
If existing FinFET structures are used, then manufacturing is simpler, but parasitic capacitance is higher reducing device performance
Solution Approach 1:
The protruding parts of the gate stack are formed during the initial gate formation process using selective etching techniques with bromine and chlorine containing gases. This preliminary structuring is done before final device assembly, allowing the gate to inherently possess reduced parasitic capacitance without requiring additional manufacturing steps later
Solution Approach 2:
The gate stack geometry is modified by changing the width parameter along the channel direction - the protruding parts have a width that is smaller than the fin width. This parameter change reduces the overlap area between the gate and source/drain regions, thereby reducing parasitic capacitance while maintaining ease of manufacture through standard lithography and etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves yield and device performance by reducing parasitic capacitance and increasing carrier mobility through strained material portions and optimized gate stack profiles.
Implementation Method 1
the creation of a dummy gate stack using bromine and chlorine containing etching gases
Data Source
AI summary
A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.