FinFET Gate Recess Isolation With Low-k Dielectric Layers
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity and difficulty of fabrication processes as feature sizes continue to decrease, necessitating improved manufacturing methods.
Innovation Solution
A method involving the formation of semiconductor fins with epitaxial source/drain structures and advanced gate structures, utilizing multi-patterning processes and specific materials like boron nitride for dielectric layers to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process difficulty increases and reliability decreases
Solution Approach 1:
The patent introduces strain engineering by modifying the crystal structure parameters of the semiconductor layer through selective epitaxial growth on patterned substrates with different crystal orientations. This changes the physical parameters of the material to enhance carrier mobility and device performance at scaled dimensions
Solution Approach 2:
The patent employs composite structures combining semiconductor layers with different materials and crystal orientations in a single device architecture. This allows different regions to contribute different properties, maintaining reliability while enabling continued scaling
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases
Solution Approach 1:
The patent segments the substrate into regions with different crystal orientations before epitaxial growth, allowing different semiconductor layers to be formed with distinct properties. This segmentation enables complex device functionality to be achieved through material differentiation rather than complex processing steps
Solution Approach 2:
The patent performs preliminary patterning of the substrate to create regions with different crystal orientations before the main epitaxial growth process. This preliminary action simplifies subsequent fabrication steps by pre-establishing the structural framework needed for complex devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances carrier mobility and improves the reliability and performance of semiconductor devices by strain-stressed epitaxial source/drain structures and optimized dielectric materials, addressing the challenges of miniaturization in semiconductor fabrication.
Implementation Method 1
strain-stressed epitaxial source/drain structures
Implementation Method 2
boron nitride for dielectric layers
Data Source
AI summary
A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.