FinFET Gate Formation via Dummy Gate Replacement and Insulating Structure
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing finFET transistors with precise control over fin dimensions and gate formation, leading to issues with short channel effects and leakage, particularly in achieving consistent and efficient gate filling processes.
Innovation Solution
A method involving the formation of first and second fins on a substrate, followed by the creation of dummy gate structures, their replacement with actual gate structures, and the insertion of an insulating structure between them, which allows for improved gate performance by optimizing the trench and gate dimensions and filling processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate formation processes are used, then manufacturing simplicity is maintained, but gate filling precision and control over fin dimensions deteriorate
Solution Approach 1:
The gate formation process is divided into multiple discrete steps: forming mandrels with specific dimensions, depositing first and second materials in sequence, and performing selective etching. This segmentation allows precise control over gate filling while maintaining manufacturability through standardized process modules.
Solution Approach 2:
Mandrels are formed in advance with predetermined dimensions before the actual gate structure is built. This preliminary action establishes the geometric framework that guides subsequent material deposition and etching processes, ensuring precise gate filling control.
2Productivity
If fin dimensions are reduced to increase device density, then higher device density is achieved, but short channel effects and leakage increase
Solution Approach 1:
Different materials with distinct etching selectivities are used in specific locations: a first material is deposited conformally on the mandrel, then a second material is deposited and selectively etched to form the gate structure. This local differentiation of material properties enables precise control of fin dimensions and gate geometry, reducing short channel effects while maintaining high device density.
Solution Approach 2:
The process utilizes changes in material parameters (etching selectivity, deposition conformality) to control the final gate structure dimensions. By selecting materials with appropriate etching characteristics and controlling deposition parameters, precise fin and gate dimensions are achieved, mitigating short channel effects.
3Manufacturing precision
If complex multi-material deposition is used, then gate filling control is improved, but manufacturing complexity increases
Solution Approach 1:
Within each deposition step, uniform and conformal material coverage is achieved across the substrate. The first material is deposited homogeneously to form a complete mandrel coating, and the second material is deposited homogeneously for selective removal. This homogeneity simplifies process control while maintaining precision.
Solution Approach 2:
The process incorporates feedback through selective etching where the second material is deposited and then selectively removed based on its distinct etching characteristics. This feedback mechanism allows precise control of gate filling by removing excess material in controlled steps, balancing precision with manufacturability.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming first and second fins over a substrate, forming first and second dummy gate structures over the first and second fins, respectively, replacing the first and second dummy gate structures with first and second gate structures, respectively, and after replacing the first and second dummy gate structures, forming an insulating structure between the first and second gate structures.