Fin FET Gate Replacement with Separation Plugs
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing high-aspect-ratio fin field effect transistors (Fin FETs) due to complexities in gate replacement technology, particularly in achieving reliable and efficient formation of metal gate structures with high-k gate dielectrics, which affects device performance and reliability.
Innovation Solution
The process involves forming fin structures over a substrate, followed by the sequential deposition and patterning of insulating and gate layers, including the use of high-k dielectric materials and metal gate electrodes, with the introduction of separation plugs to ensure proper alignment and filling of metal gate materials without voids, enhancing the manufacturing efficiency and reliability of Fin FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate replacement technology is used to form metal gate structures with high-k gate dielectrics, then device performance and reliability are improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is segmented into distinct functional layers: high-k dielectric layer for electrical isolation and metal gate electrode layer for electrical control. This segmentation allows each layer to be optimized independently for its specific function, improving device reliability while enabling systematic manufacturing processes.
Solution Approach 2:
The high-k dielectric layer is formed preliminary before the metal gate electrode layer. This preliminary action ensures proper alignment and interface quality between layers, which is critical for device performance. The sequential deposition process prevents void formation and ensures complete coverage.
2Productivity
If high-aspect-ratio fin structures are manufactured, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The gate structure extends in multiple dimensions, wrapping around the vertical fin structure. This three-dimensional gate configuration provides superior channel control compared to planar gates, enabling higher device density through increased effective gate width while maintaining manufacturability through conformal deposition processes.
Solution Approach 2:
The high-k dielectric layer parameters (thickness, dielectric constant) are optimized to provide sufficient electrical isolation for high-aspect-ratio fins. The metal gate electrode parameters (thickness, material composition) are adjusted to ensure complete filling of high-aspect-ratio spaces without voids, achieving both high device density and manufacturing precision.
3Reliability
If metal gate materials are filled in high-aspect-ratio structures, then gate control improves, but void formation increases
Solution Approach 1:
The high-k dielectric layer serves as an intermediary between the fin structure and metal gate electrode. This intermediate layer provides a conformal template that guides metal gate material deposition, ensuring complete filling of high-aspect-ratio spaces. The intermediary layer prevents direct contact between metal and fin, improving gate control while enabling void-free filling through its conformal geometry.
Solution Approach 2:
The high-k dielectric layer is formed preliminary to provide a complete conformal template before metal gate deposition. This preliminary conformal layer ensures that subsequent metal filling follows the desired geometry precisely, preventing void formation in high-aspect-ratio structures while maintaining superior gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of Fin FETs with improved performance and reliability by ensuring proper alignment and filling of metal gate structures, reducing voids and enhancing the integration of high-k dielectric materials, thus addressing the challenges in existing gate replacement technologies.
Implementation Method 1
a high-k gate dielectric having a high electric dielectric constant is often used in Fin FET device
Implementation Method 2
A metal gate structure together with a high-k gate dielectric having a high electric dielectric constant is often used in Fin FET device
Data Source
AI summary
A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.