FinFET Gate Electrode Residue Reduction via Fin Spacing
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Solution Overview
Problem
The formation of FinFETs adjacent to each other leads to gate electrode residue issues due to uneven photoresist thickness, causing potential short circuits and circuit failure, as the gate electrode layer is not flat, resulting in incomplete etching and residue formation.
Innovation Solution
Reducing the fin space between neighboring FinFETs to less than twice the gate height, ensuring the gate electrodes have a height greater than half the fin space, which allows for a more planar gate electrode layer and eliminates the need for additional planarization processes, thereby preventing residue formation and ensuring electrical disconnection between gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If FinFETs are formed adjacent to each other with standard fin spacing, then area usage is improved, but gate electrode residue forms due to uneven photoresist thickness causing short circuits
Solution Approach 1:
The patent changes the fin spacing parameter to be less than twice the gate height, which fundamentally alters the topography of the gate electrode layer. This parameter change ensures that the photoresist can be applied with sufficient uniformity during lithography, preventing residue formation while maintaining high area usage efficiency.
Solution Approach 2:
By reducing fin spacing, the patent creates a more equipotential (flat) surface for the gate electrode layer across different fin regions. This eliminates the height differences that cause uneven photoresist thickness, ensuring uniform etching and preventing gate electrode residue that would otherwise short adjacent gates.
2Manufacturing precision
If fin space is reduced to less than twice the gate height, then manufacturing precision is improved by eliminating gate electrode residue, but device complexity increases due to tighter spacing requirements
Solution Approach 1:
The patent establishes a specific parameter relationship (fin space < 2 × gate height) that simplifies the manufacturing process by eliminating the need for additional planarization steps. While spacing control becomes tighter, the overall process complexity is reduced by removing residue-prone topography variations.
3Ease of manufacture
If gate electrode layer is made non-flat to follow fin topography, then ease of manufacture is improved by direct formation, but manufacturing precision deteriorates due to photoresist thickness variation
Solution Approach 1:
Instead of making the gate electrode layer non-flat to follow fin topography, the patent inverts the approach by controlling fin spacing to create a flat gate electrode layer. This maintains ease of manufacture through direct blanket formation while achieving photoresist thickness uniformity necessary for precise patterning.
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.