FinFET Metal Gate Stack With Low-Resistivity Layer for Gate Resistance
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Solution Overview
Problem
The poly-depletion effect in conventional polysilicon gates increases the effective gate dielectric thickness, making it difficult to create an inversion layer in semiconductor devices, leading to higher gate resistance in Fin Field-Effect Transistors (FinFETs).
Innovation Solution
A low-resistivity conductive layer is formed over a recessed metal gate in FinFETs, reducing the overall gate resistance by having a resistivity lower than the metal gate layers, which involves a series of etching and deposition processes to create a metal gate stack with a low-resistivity metal layer, such as tungsten, over the high-resistivity work-function and blocking layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional polysilicon gate is used, then the gate structure is simple, but the poly-depletion effect increases the effective gate dielectric thickness and raises gate resistance
Solution Approach 1:
The gate electrode is divided into multiple metal layers with different resistivities. A first metal layer with lower resistivity is positioned closer to the gate dielectric, while a second metal layer with higher resistivity is positioned farther away. This segmentation reduces overall gate resistance while maintaining structural organization and avoiding the poly-depletion effect inherent in polysilicon gates.
Solution Approach 2:
The gate electrode uses a composite structure combining multiple metal materials with different electrical properties. The first metal layer (e.g., tungsten, cobalt, or copper) provides low resistivity for reduced gate resistance, while the second metal layer (e.g., tungsten or titanium nitride) provides structural support and work function adjustment. This composite approach achieves both low resistance and structural integrity without using polysilicon.
2Reliability
If multiple metal layers are deposited to form a metal gate, then gate resistance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The first metal layer with lower resistivity is deposited and patterned before the second metal layer. This preliminary action establishes the low-resistance pathway close to the gate dielectric first, then the second metal layer is added subsequently for structural completion. This sequence simplifies the overall manufacturing by establishing the critical low-resistance path early in the process.
Solution Approach 2:
Different metal layers are strategically positioned at different locations within the gate electrode structure. The first metal layer with lower resistivity is placed closer to the gate dielectric where it most effectively reduces gate resistance, while the second metal layer with higher resistivity is placed farther away where it provides structural support. This local optimization achieves maximum resistance reduction with minimal process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a low-resistivity conductive layer significantly reduces the gate resistance of short-channel transistors to about 10% of the original resistance, improving transistor performance by reducing the poly-depletion effect and enhancing inversion layer formation.
Implementation Method 1
a first low-resistance metal layer overlapping and contacting the work-function layer and the blocking layer... The first low-resistance metal layer has a first resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer
Data Source
AI summary
A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.