FinFET Gate Electrode with Round Inclined Surface for Leakage Reduction
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Solution Overview
Problem
Integrated circuit devices with multi-gate structures face challenges in reducing the short channel effect and preventing undesired connections between the source/drain region and the gate electrode, leading to reliability issues and increased leakage currents.
Innovation Solution
The design incorporates a fin-type active region with a gate electrode that includes a main gate electrode and sub-gate electrodes, surrounded by spacer structures, with a round inclined surface at the bottom portion of the main gate electrode, which reduces the separation distance between the source/drain regions and the gate electrode, thereby minimizing leakage currents and preventing undesired connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to provide good performance and economical prices, then productivity and cost-effectiveness are improved, but the short channel effect occurs causing reduction in reliability
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a multi-gate structure (such as FinFET or nanosheet) that extends the gate into the vertical dimension. This dimensional change allows the gate to control the channel from multiple directions (top and sidewalls), effectively suppressing the short channel effect while maintaining high integration density. The gate electrode wraps around the channel region, providing enhanced electrostatic control without increasing the planar footprint.
2Length of moving object
If the interval between source region and drain region is reduced to minimize spacing, then area is reduced improving integration, but undesired connection between source/drain region and gate electrode may occur
Solution Approach 1:
The patent introduces a round inclined surface at the bottom portion of the main gate electrode instead of a conventional flat or sharp-cornered structure. This curved geometry reduces stress concentration and prevents direct contact between the source/drain regions and the gate electrode, eliminating undesired connections while allowing minimal spacing between source and drain regions. The rounded profile creates a natural clearance that maintains electrical isolation.
3Ease of manufacture
If conventional flat gate structure is used, then manufacturing is simpler, but leakage currents increase and electrical characteristics deteriorate
Solution Approach 1:
The round inclined surface at the bottom of the main gate electrode eliminates sharp corners that act as stress concentration points and sources of leakage currents. The curved geometry distributes electric field more uniformly, reducing band-to-band tunneling and other leakage mechanisms. This structural modification improves electrical characteristics while remaining compatible with standard semiconductor manufacturing processes.
Solution Approach 2:
The patent modifies the geometric parameters of the gate electrode by introducing an inclined surface with a specific curvature radius. This parameter change from a flat structure to a curved structure with controlled radius of curvature optimizes the electric field distribution, reduces leakage currents, and improves carrier injection efficiency without significantly complicating the manufacturing process.
Data Source
AI summary
An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.