FinFET Gate Structure With Sacrificial Layer for Leakage Control
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Solution Overview
Problem
FinFET devices face high leakage current due to short-channel effects as feature sizes become finer, deteriorating device performance.
Innovation Solution
A semiconductor device design featuring a fin structure with a sacrificial layer pattern, dielectric layer, and gate electrode structure, where the sacrificial layer is made of silicon germanium and the gate electrode covers both the upper surface and sidewall of the epitaxial layer, reducing leakage current through the interposition of a dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are reduced to improve device scaling, then transistor density increases, but leakage current increases due to short-channel effects
Solution Approach 1:
The patent transitions from planar 2D channel to 3D fin-shaped channel, adding vertical dimension to the transistor structure. This dimensional change increases the effective channel area for current conduction while maintaining control over the channel, thereby improving transistor density without proportionally increasing leakage current as occurs in scaled planar devices
Solution Approach 2:
The gate electrode is divided into multiple segments: a first gate electrode on the upper surface of the fin structure and a second gate electrode on the sidewall. This segmentation allows independent optimization of each gate region, enabling better control over the channel and reduced leakage current through selective gating regions
2Object-generated harmful factors
If a gate electrode structure is added on the sidewall to reduce leakage current, then leakage current decreases, but device structure becomes more complex
Solution Approach 1:
The fin structure serves multiple functions simultaneously: it provides the channel region for current conduction, acts as a support structure for both gate electrodes, and enables the three-dimensional configuration that reduces leakage. This multi-functionality reduces the need for additional separate components that would increase device complexity
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a fin structure on a substrate. A sacrificial layer pattern is formed on the fin structure. An active layer pattern is formed on the sacrificial layer pattern. A dummy gate pattern is formed on the active layer pattern. A spacer is formed on the dummy gate pattern. A source/drain structure is formed on the active layer pattern using an epitaxial growth process. An interlayer dielectric layer is formed on the dummy gate pattern and the active layer pattern. The interlayer dielectric layer is planarized to expose the dummy gate pattern. The dummy gate pattern is removed to expose the active layer pattern and the sacrificial layer pattern. The exposed sacrificial layer pattern is removed to form a through-hole between the exposed active layer pattern and the fin structure, the second portion of the sacrificial layer pattern is not removed.