FinFET Gate Replacement with Hydrophobic SAM Surface Treatment
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Solution Overview
Problem
In the semiconductor industry, the fabrication of fin field effect transistors (Fin FETs) with high aspect ratio semiconductor fins faces challenges in achieving precise control over the gate structure and dielectric layers, leading to inefficiencies in surface area utilization and resistance, particularly due to the limitations in the hydrophobicity control of surfaces during the manufacturing process.
Innovation Solution
The implementation of a self-assembled monolayer (SAM) to modify the hydrophobicity of surfaces, allowing for selective formation of dielectric and conductive layers without conformal deposition on hydrophobic regions, thereby minimizing gate space reduction and optimizing the volume for the gate electrode, and reducing the distance between the separation plug and channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate replacement technology is used to form metal gate structures in Fin FETs, then the gate structure can be formed, but the control over hydrophobicity of surfaces is limited, leading to inefficient surface area utilization and increased resistance
Solution Approach 1:
The patent applies parameter changes by modifying the hydrophobicity of dielectric material surfaces through self-assembled monolayer (SAM) treatment. This chemical parameter change enables selective area deposition by creating hydrophobic regions that repel aqueous precursor solutions, thereby controlling where dielectric and conductive layers form. This resolves the contradiction by achieving precise hydrophobicity control to improve manufacturing precision while enhancing device reliability through optimized gate structure formation.
Solution Approach 2:
The patent introduces self-assembled monolayers (SAMs) as intermediary substances between the dielectric material surfaces and the deposition process. These SAMs act as mediators that modify surface properties to control deposition patterns. The SAMs create hydrophobic barriers that prevent conformal deposition on specific regions, enabling selective area formation of gate structures and improving both manufacturing precision and device reliability.
2Area of stationary object
If conformal deposition is performed on all surfaces, then complete coverage is achieved, but gate space is unnecessarily reduced and the distance between separation plug and channel layer increases
Solution Approach 1:
The patent applies local quality by creating spatially varying surface properties through SAM treatment. Different regions of the dielectric material surfaces are rendered hydrophobic to different extents, enabling selective area deposition. This allows dielectric and conductive layers to form only on hydrophilic regions, preserving gate space volume while maintaining precise control over layer formation locations and thicknesses.
Solution Approach 2:
The patent changes the surface energy parameter of dielectric materials by applying self-assembled monolayers. This parameter change creates hydrophobic regions that repel deposition precursors, preventing conformal deposition on entire surfaces. The result is optimized gate space utilization with layers forming only where needed, maintaining manufacturing precision through controlled deposition on hydrophilic regions.
3Volume of stationary object
If the gate space is minimized, then device density increases, but it becomes difficult to maintain precise control over dielectric and conductive layer formation
Solution Approach 1:
The patent applies local quality by creating distinct hydrophobic and hydrophilic regions within the minimized gate space. This spatial differentiation of surface properties enables precise control over where dielectric and conductive layers form, even when the overall gate space volume is reduced. The SAM-treated hydrophobic regions act as protective zones while hydrophilic regions serve as deposition zones, maintaining manufacturing precision despite compact dimensions.
Solution Approach 2:
The patent uses self-assembled monolayers as intermediary agents that enable precise layer formation control in minimized gate spaces. The SAMs modify local surface properties to create hydrophobic barriers, ensuring that deposition occurs only in designated hydrophilic regions. This intermediary mechanism allows accurate control of dielectric and conductive layer formation even when the gate space is compacted to increase device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient filling of the gate space with the main gate electrode, reducing resistance and minimizing the gate space size, while maintaining precise control over layer formation, thus enhancing the performance and reliability of Fin FET devices.
Implementation Method 1
The surfaces of the dielectric material portions are made hydrophobic with a self-assembled monolayer before the dielectric layer and the conductive layers are formed
Data Source
AI summary
In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.