FinFET Gate Structure to Prevent Seam Voids and Work Function Oxidation
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing seam void defects and oxidation of work function layers during the gate cut process in FinFET devices, leading to increased gate resistance, threshold voltage shift, and gate dielectric leakage.
Innovation Solution
A method for forming gate structures in FinFET devices that involves forming a gate dielectric layer and work function layers within openings in the gate stack, followed by an etch process to widen the upper portions and fill with a conductive material, preventing seam void defects and oxidation, thereby reducing gate resistance and maintaining threshold voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate cut process is used, then manufacturing simplicity is maintained, but seam void defects occur leading to increased gate resistance
Solution Approach 1:
The patent performs preliminary actions by forming a mandrel structure and filling material before the gate cut process. The mandrel is positioned to prevent etchant penetration, and the fill material is deposited in advance to ensure complete filling without voids. This preliminary preparation eliminates seam void defects that would otherwise increase gate resistance.
Solution Approach 2:
The patent introduces a mandrel as an intermediary element during the gate cut process. This mandrel acts as a physical barrier that prevents etchant from penetrating into the gate stack, thereby preventing seam void defect formation. The mandrel is temporarily present during processing and is removed afterward, serving its protective function without becoming part of the final structure.
2Reliability
If gate cut process is performed, then device integration is achieved, but oxidation of work function layers occurs leading to threshold voltage shift
Solution Approach 1:
The patent creates a protective environment by filling the gate structure with inert or reactive fill material that prevents oxidation. The fill material, such as tungsten or other metals, occupies the space that would otherwise be exposed to oxidizing conditions during the gate cut process. This eliminates oxidation of work function layers and maintains threshold voltage stability.
Solution Approach 2:
The fill material serves as an intermediary that protects the work function layer from oxidation during the gate cut process. By filling the structure with material that resists oxidation, the work function layer is indirectly protected without requiring direct modification of the gate cut process itself.
3Reliability
If gate cut process is performed, then device integration is achieved, but gate dielectric leakage and breakdown occur
Solution Approach 1:
The patent performs preliminary filling of the gate structure with conductive or insulating material before the gate cut process. This fill material prevents etchant from reaching and damaging the gate dielectric layer. By preparing the structure in advance with protective fill material, the gate dielectric is shielded from leakage and breakdown risks during subsequent processing.
Solution Approach 2:
The patent applies a form of cushioning protection by introducing fill material that absorbs or deflects potential damage to the gate dielectric. The fill material acts as a cushion between the etchant and the gate dielectric, preventing direct contact and potential damage that would lead to leakage or breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces seam void defects and oxidation issues, leading to improved gate resistance and threshold voltage stability, while preventing gate dielectric leakage and breakdown.
Implementation Method 1
an etch process to widen the upper portions
Implementation Method 2
fill with a conductive material
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.