FinFET Gate Stack Segmentation for Density and Precision
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher device density, performance, and lower costs, particularly in the fabrication and design of FinFET devices, where the reduction of dimensions and integration of high-k metal gate processes are complex and require innovative manufacturing methods.
Innovation Solution
A method for manufacturing semiconductor devices involves forming semiconductor fins on a substrate, creating gate dielectrics and dummy gate layers, patterning and recessing the fins to form source/drain and channel regions, and using epitaxy to strain the channels for enhanced carrier mobility, followed by the formation of work function conductors and filling conductors with plug and cap portions to increase contact areas and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of FinFETs are progressively reduced to increase device density, then device density increases, but manufacturing precision and process control become more difficult
Solution Approach 1:
The gate electrode is divided into multiple segments with different work function materials (first gate electrode with first work function material, second gate electrode with second work function material). This segmentation allows independent optimization of different gate regions to achieve desired threshold voltages while maintaining compatibility with standard CMOS processes, thereby enabling higher device density without compromising manufacturing precision
Solution Approach 2:
Different regions of the gate electrode are assigned different work function materials based on local requirements. The first gate electrode region uses a first work function material optimized for specific threshold voltage characteristics, while the second gate electrode region uses a second work function material for complementary characteristics. This local quality approach enables precise control of device electrical properties at each location, facilitating higher density integration with maintained fabrication precision
2Reliability
If high-k metal gate processes are integrated to improve device performance, then carrier mobility and device performance increase, but device complexity and process difficulty increase
Solution Approach 1:
The gate electrode structure uses homogeneous material layers (first work function material layer and second work function material layer) that can be deposited using standard sputtering or evaporation processes. This homogeneity in material selection and deposition methodology simplifies the integration of high-k metal gate processes into existing CMOS fabrication lines, reducing process complexity while maintaining enhanced device performance
Solution Approach 2:
The invention changes the work function parameter of the gate electrode by selecting materials with appropriate work functions (e.g., tungsten for first gate electrode, aluminum or copper for second gate electrode). This parameter change enables optimization of threshold voltages and carrier mobility without fundamentally altering the fabrication process flow, thereby improving device performance while controlling process complexity
3Reliability
If work function conductors with plug and cap portions are formed to increase contact areas, then device performance and carrier mobility improve, but manufacturing steps and process time increase
Solution Approach 1:
The first and second work function material layers are merged to form a continuous gate electrode structure that spans across the semiconductor fin. This merging eliminates the need for separate processing of discrete gate segments, reducing the number of manufacturing steps and associated cycle time while maintaining the beneficial effects of having multiple work function materials for optimized carrier mobility and device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance FinFET devices with increased carrier mobility and contact areas, addressing the challenges of device density and cost while enhancing manufacturing efficiency.
Implementation Method 1
performing epitaxy to strain the channels
Data Source
AI summary
A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.