FinFET Gate Formation via Segmented Preliminary Gates
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Solution Overview
Problem
The formation of gate electrodes in semiconductor devices is hindered by the height difference between P-type and N-type channel regions, leading to issues during the Chemical Mechanical Polishing (CMP) process.
Innovation Solution
The semiconductor device design includes a substrate with PMOS and NMOS regions, where the upper end of the first active region extends to a lower level than the second active region, allowing for gate electrodes to be formed at specific levels, with a semiconductor layer on the first active region and a gate dielectric layer surrounding the gate electrodes, facilitating a simplified process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P-type and N-type channel regions are formed with different heights to optimize device performance, then device performance is improved, but the formation of gate electrodes becomes difficult and the CMP process encounters problems
Solution Approach 1:
The invention divides the gate electrode structure into two separate preliminary gates (first preliminary gate on N-type fin, second preliminary gate on P-type fin) that are formed independently at different stages, allowing each to be optimized for its specific fin height without interfering with the other
Solution Approach 2:
The invention performs preliminary gate formation on each fin type before the other fin is fully processed, allowing the channel regions to be formed at different heights without compromising subsequent gate electrode formation. The first preliminary gate is formed on the N-type fin before the P-type fin is created, and vice versa
2Adaptability or versatility
If channel SiGe layer is formed on N-type fin using SEG technique to create different heights, then device functionality is enhanced, but height difference causes problems in CMP process
Solution Approach 1:
The channel SiGe layer is formed on the N-type fin using SEG technique before the P-type fin is created, allowing the N-type fin to develop its full height with the SiGe layer. When the P-type fin is subsequently formed, it naturally achieves a different height, and the preliminary gate structure already in place accommodates this height difference without causing CMP process problems
3Ease of manufacture
If first and second preliminary gates are formed at different stages on different fins, then gate electrode formation is enabled, but process complexity increases
Solution Approach 1:
The invention merges the formation of both preliminary gates and both source/drain regions into a unified multi-stage process flow. The first preliminary gate and first source/drain are formed on the N-type fin, then the second preliminary gate and second source/drain are formed on the P-type fin, with both sequences ultimately converging to form the final gate electrodes through trench formation and gate filling
Solution Approach 2:
The process performs preliminary gate formation on one fin type before processing the other fin type, allowing each preliminary gate to be optimized for its specific fin characteristics. This preliminary action enables the subsequent formation of source/drain regions and final gate electrodes without conflicts arising from height differences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the formation of gate electrodes by ensuring consistent heights and shapes, improving the CMP process and overall semiconductor device fabrication.
Implementation Method 1
A channel SiGe layer may be formed on the N-type fin using a Selective Epitaxial Growth (SEG) technique
Data Source
AI summary
A semiconductor device has active regions with different conductivity types. A substrate has a PMOS region and an NMOS region. A first active region is in the PMOS region. A second active region is in the NMOS region. A semiconductor layer is on the first active region. A first gate electrode crosses the first active region and extends on the semiconductor layer. A second gate electrode is on the second active region. An upper end of the first active region extends to a level lower than an upper end of the second active region. A lower end of the first active region extends to a level lower than a lower end of the second active region.