FinFET Gate Separation Layer to Prevent Gate Bridging
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices deteriorates their operating characteristics, necessitating improved manufacturing methods to enhance performance and overcome integration limitations.
Innovation Solution
A semiconductor device design featuring first and second gate patterns separated by a separation pattern, with each gate pattern comprising high-k dielectric and metal-containing layers, and a method involving sequential removal of high-k dielectric and metal-containing layers to form distinct gate patterns, ensuring no exposure on the separation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are scaled down to increase integration density, then device density improves, but operating characteristics deteriorate
Solution Approach 1:
The gate pattern is segmented into multiple layers including a first gate electrode pattern and a second gate electrode pattern separated by a separation layer. This segmentation allows each layer to be optimized independently, maintaining electrical performance while achieving higher integration density through compact spacing.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional stacked gate structure with vertical separation. By utilizing the vertical dimension with the separation layer between gate electrode patterns, the design achieves higher density without compromising the horizontal operating characteristics of each transistor.
2Productivity
If gate patterns are placed closer together to increase density, then integration improves, but bridge or short formation between gates increases
Solution Approach 1:
A separation layer is introduced as an intermediary between the first gate electrode pattern and the second gate electrode pattern. This separation layer acts as a protective barrier that prevents direct contact and potential short circuits between adjacent gates, enabling closer spacing while maintaining electrical isolation.
Solution Approach 2:
The separation layer is formed as part of the gate structure fabrication process itself, providing inherent electrical isolation without requiring additional external protective structures. The layer serves dual purposes: maintaining spacing for density and providing electrical insulation to prevent shorts.
Data Source
AI summary
A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern and the second gate pattern being spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern includes a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern, the first metal-containing pattern covering a sidewall of the first high-k dielectric pattern. The second gate pattern includes a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern, and the separation pattern is in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern.