FinFET Gate Separation via Selective Etching
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Solution Overview
Problem
The fabrication of FinFETs with separate gates is complex, sensitive to process variations, and costly, especially when integrating different gate-electrode materials, as existing methods require tedious and misalignment-sensitive CMP treatments, making it challenging to differentiate between FinFETs with separate and continuous gates on a single wafer.
Innovation Solution
A method involving a basic FinFET structure with a continuous gate stack, where a contact opening is created to selectively remove sections of the first gate layer, forming a tunnel, and depositing a second gate-isolation layer to create a gate-separation layer, allowing for the formation of separate gate electrodes with improved tolerance to process variations and flexibility in material choice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP treatment is used to separate gates into two gate layers, then FinFETs with separate gates can be fabricated, but the process becomes very sensitive to process variations and misalignment
Solution Approach 1:
The patent introduces a sacrificial layer (e.g., silicon nitride) as an intermediary between the gate dielectric and the gate electrode. This sacrificial layer is deposited conformally over the fin structure, then selectively removed via etch holes to define separate gate regions. The sacrificial layer acts as a temporary mediator that enables precise gate separation without requiring sensitive CMP processes, as it can be removed selectively through chemical etching after the gate electrode is formed.
Solution Approach 2:
The gate electrode is formed continuously over the entire fin structure before the sacrificial layer is removed. This preliminary formation of the continuous gate electrode allows subsequent selective removal of the sacrificial layer to create separate gates, rather than attempting to separate gates during the electrode formation process itself. This preliminary action simplifies the overall process by decoupling electrode formation from gate separation.
2Adaptability or versatility
If CMP treatment is used to separate gates, then separate gate FinFETs can be created, but it affects the whole wafer and does not allow differentiating between FinFETs of different types
Solution Approach 1:
The patent enables local differentiation of FinFET types by allowing selective removal of the sacrificial layer in specific regions. Etch holes can be formed only in regions where separate gates are desired, while other regions maintain continuous gates. This local application of the gate separation process allows mixing different FinFET types on the same wafer without requiring separate fabrication runs, as each region can be independently configured.
Solution Approach 2:
The wafer is segmented into different regions with different gate configurations through selective processing. By controlling where etch holes are formed and where the sacrificial layer is removed, the patent enables segmentation of the wafer into regions with separate-gate FinFETs and regions with continuous-gate FinFETs, all within a single unified fabrication process.
3Reliability
If protective dielectric cap and thermal growth are used for gate isolation, then gate separation can be achieved, but the processing becomes tedious and expensive
Solution Approach 1:
The patent replaces the mechanical CMP process with a chemical etching process for gate separation. Instead of using mechanical polishing to remove material and separate gates, the invention uses chemical etching of the sacrificial layer through selectively formed etch holes. This substitution eliminates the need for CMP equipment and processes, simplifying the fabrication line and improving productivity while maintaining reliable gate isolation through the conformally deposited sacrificial layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication of FinFETs with separate gates, reduces sensitivity to misalignments, and allows for the use of different gate materials, enabling efficient integration of both separate and continuous gate FinFETs on a single wafer, optimizing integrated circuit design and performance.
Implementation Method 1
fabricating a first contact opening that extends through the cover layer to the contact section of the first gate layer; selectively, with respect to at least the cover layer and the substrate, removing through the first contact opening the first gate layer in the contact section
Implementation Method 2
depositing a second gate-isolation layer on the tunnel walls, thus also forming a gate-separation layer on the end wall of the first tunnel
Data Source
AI summary
The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling.