FinFET Gate Separation Plug for Void-Free Metal Filling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor fabrication technologies face challenges in efficiently forming three-dimensional fin structures for Fin FET devices, particularly in ensuring complete filling of metal gate materials without voids and achieving smaller device dimensions.
Innovation Solution
The method involves forming a separation plug made of insulating material to separate metal gate structures, eliminating the need for gate dielectric and underlying metal layers on the separation plug's side surface, allowing for larger gate openings and complete filling of metal gate materials without voids, thereby enabling smaller device dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate dielectric and underlying metal layers are formed on the separation plug side surface, then the gate structure is complete, but the device dimensions cannot be reduced and void formation occurs
Solution Approach 1:
The patent removes the gate dielectric and underlying metal layers from the separation plug side surface, extracting only the necessary components from the gate structure. This extraction eliminates the space occupation that prevented device shrinkage and removed the source of void formation, allowing complete metal gate material filling while achieving smaller device dimensions.
2Productivity
If gate openings are made smaller to increase device density, then device dimensions are reduced, but metal gate materials cannot be completely filled without voids
Solution Approach 1:
The separation plug acts as an intermediary structure that mediates between the conflicting requirements of small gate openings and complete material filling. By removing gate dielectric and underlying metal layers from the separation plug side surface, the plug creates a clean interface that enables complete metal gate material infiltration into the gate opening without void formation, even at reduced device dimensions.
3Device complexity
If the gate structure is simplified by removing layers, then manufacturing complexity is reduced, but the gate structure completeness is compromised
Solution Approach 1:
The patent applies local quality by selectively removing gate dielectric and underlying metal layers only from the separation plug side surface, while maintaining these layers in other critical areas of the gate structure. This localized modification simplifies the specific region causing manufacturing complexity while preserving the overall gate structure integrity and functionality.
Data Source
AI summary
A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.