FinFET Gate Structure With Sloped Lower Sidewalls to Prevent Shorting
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Solution Overview
Problem
Existing FinFET devices face challenges with the protrusion of gate electrode layers, leading to electrical shorting and performance degradation, particularly exacerbated in the edge regions of semiconductor wafers during the fabrication process.
Innovation Solution
The formation of a gate structure with an upper portion having vertical sidewalls and a lower portion with sloped sidewalls, where the upper portion has a wider top surface than the lower portion's bottom surface, to prevent protrusion and ensure proper filling of the gate electrode layer, thereby improving the FinFET device's performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is formed over the fin structure, then the device fabrication process is simple, but the gate electrode layer protrudes causing electrical shorting and performance degradation
Solution Approach 1:
The gate structure is divided into two distinct portions: an upper gate portion and a lower gate portion. The upper gate portion has vertical sidewalls that align with the fin structure, while the lower gate portion has sloped sidewalls that extend beyond the fin. This segmentation prevents protrusion of the gate electrode layer while maintaining fabrication simplicity.
Solution Approach 2:
The gate structure employs asymmetric geometry where the upper gate portion has a different width than the lower gate portion. Specifically, the upper gate portion has a first width and the lower gate portion has a second width that is greater than the first width, creating a stepped configuration that prevents electrode layer protrusion.
2Manufacturing precision
If the gate electrode layer is filled to the top of the fin structure, then complete gate coverage is achieved, but protrusion occurs leading to electrical shorting
Solution Approach 1:
The gate structure is pre-configured with a lower gate portion that has sloped sidewalls extending beyond the fin structure. This preliminary configuration creates a recessed region where the gate electrode layer can be filled without protruding, preventing electrical shorting before the filling process occurs.
Solution Approach 2:
The lower gate portion with sloped sidewalls acts as an intermediary structure between the fin structure and the gate electrode layer. It provides a transition zone that prevents direct contact and potential shorting between the gate electrode and surrounding structures.
3Reliability
If the gate structure is formed with uniform width, then fabrication is simpler, but drain-induced barrier lowering effects are not reduced
Solution Approach 1:
The gate structure implements local quality variations where the upper gate portion has a narrower width compared to the lower gate portion. This localized width variation specifically addresses drain-induced barrier lowering effects in the critical region while maintaining easier fabrication through the overall two-port ion design.
Data Source
AI summary
A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width.