FinFET Gate Spacer Layout for Easier Contact Alignment
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Solution Overview
Problem
The formation and alignment of minute features such as gates and contacts in integrated circuits, particularly in FinFETs, are challenging due to the complexity and precision required, leading to issues like increased circuit area, variability, and reduced yield.
Innovation Solution
The technique involves forming thinner gate spacers alongside the gates, omitting gate structures where thicker spacers are present, and using conductive caps to electrically couple gate structures on either side of the fins, which simplifies the fabrication and alignment of contacts, reduces gate capacitance, and enhances device switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional planar gate structures are used, then fabrication is simpler, but contact alignment becomes increasingly difficult and circuit area increases as device sizes shrink
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional FinFET gate structures that wrap around vertical fins. This dimensional change provides wider recesses alongside the fins for contact formation, improving alignment precision while maintaining fabrication feasibility through self-aligned processes.
Solution Approach 2:
The gate structure is segmented into multiple portions: a first gate portion wrapping around the fin and a second gate portion extending alongside the fin. This segmentation creates distinct regions that facilitate precise contact alignment in the wider recesses while keeping the overall fabrication process manageable.
2Reliability
If gate structures are provided over the entire fin length, then electrical coupling is improved, but gate capacitance increases and switching speed decreases
Solution Approach 1:
The gate structure is divided into a first gate portion that provides electrical coupling around the fin and a second gate portion that extends alongside the fin without providing electrical coupling. This segmentation reduces gate capacitance while maintaining necessary electrical coupling through the first portion.
Solution Approach 2:
Different portions of the gate structure have different functions: the first gate portion provides electrical coupling for reliability, while the second gate portion provides structural support and spacing without adding capacitance. This local differentiation optimizes both electrical performance and switching speed.
3Ease of manufacture
If standard gate spacer thickness is used, then fabrication is straightforward, but contact formation space is limited and alignment becomes difficult
Solution Approach 1:
The FinFET structure creates vertical fins that extend upward from the substrate, providing additional horizontal space alongside the fins. Standard thickness gate spacers placed in this three-dimensional geometry create wider recesses, providing sufficient contact formation space while maintaining straightforward fabrication processes.
Data Source
AI summary
Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.