FinFET Gate Spacer Acute Angle Design for Short-Channel Effect
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Solution Overview
Problem
As semiconductor devices become smaller, they face challenges such as the short-channel effect, which affects device characteristics, and existing technologies struggle to maintain excellent electrical properties in fin field effect transistors (FinFETs) with increasing integration levels.
Innovation Solution
A semiconductor device design featuring active fins on a substrate with a gate structure and spacers where the gate structure's side wall forms an acute angle with the substrate, and the gate spacer's inner side wall is inclined to form an acute angle with its bottom surface, providing a trapezoidal cross-section and preventing electrical short failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device size is reduced to increase integration level, then the integration level is improved, but the electrical properties deteriorate due to short-channel effect
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel width without increasing the lateral footprint, thereby improving integration density while maintaining electrical control through the vertical fin geometry that reduces short-channel effects
Solution Approach 2:
The gate structure is designed with asymmetric dimensions where the gate width at the top differs from the gate width at the bottom, creating a trapezoidal cross-section. This asymmetry optimizes the gate control over the channel while accommodating the fin geometry, improving both electrical characteristics and packing density
2Reliability
If the gate structure width is reduced to improve device characteristics, then the device characteristics are improved, but the manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent forms the fins and device isolation structures before forming the gate structure. This preliminary action establishes a robust foundation that defines the eventual gate dimensions, making the gate width more controllable during subsequent formation steps and improving manufacturing precision
Solution Approach 2:
The patent employs a trapezoidal gate cross-section where the width varies through the vertical dimension, with the top width different from the bottom width. This parameter change in gate dimensions allows optimization of electrical characteristics while providing manufacturing tolerance, as the varying width compensates for fabrication variations
3Reliability
If the gate structure is made narrower to improve electrical properties, then the electrical properties are improved, but the device becomes more susceptible to electrical short failures
Solution Approach 1:
The patent introduces vertical fins that extend upward from the substrate, creating a three-dimensional channel region. This dimensional change allows the gate to maintain a narrow lateral footprint while providing sufficient control over the channel, reducing electrical short risks without compromising electrical properties
Solution Approach 2:
The asymmetric trapezoidal gate structure with different top and bottom widths provides enhanced gate control at the channel interface while maintaining adequate spacing at other regions. This asymmetry reduces susceptibility to electrical shorts by optimizing the electric field distribution throughout the device structure
Data Source
AI summary
A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.