FinFET Gate Spacer Composition for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, leading to issues such as increased parasitic capacitance in FinFETs, which affects performance in applications like ring oscillators and SRAM cells.
Innovation Solution
The formation of transistors with multi-layered gate spacers composed of silicon oxycarbonitride, which have high etch selectivity and reduced relative permittivity, thereby minimizing etching losses and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The patent changes the material composition parameters of gate spacers by forming multiple layers with different silicon oxycarbonitride compositions (varying ratios of Si, O, C, and N). This allows optimization of electrical properties to reduce parasitic capacitance while maintaining the scaled dimensions required for high integration density
Solution Approach 2:
The patent uses composite structures by forming multi-layered gate spacers where each layer has a different composition of silicon oxycarbonitride. The combination of layers with varying compositions (some richer in silicon, others in oxygen, carbon, or nitrogen) creates a composite material system that achieves both low parasitic capacitance and high etch selectivity
2Ease of manufacture
If conventional single-layer gate spacers are used, then manufacturing is simpler, but etching losses occur and parasitic capacitance is not minimized
Solution Approach 1:
The patent applies local quality by creating gate spacer layers with different compositions at different locations (layers 72A-72D with varying Si, O, C, N ratios). Each layer has tailored properties: some layers are optimized for etch selectivity while others are optimized for low permittivity, allowing precise control of etching losses without complicating the overall manufacturing process
Data Source
AI summary
In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.