FinFET Gate Spacer Height Control for Source/Drain Merging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high performance without defects, particularly in the design and manufacturing of fin field effect transistors (finFETs) and gate-all-around field effect transistors (GAAFETs), where the integration of fin structures, gate spacers, and source/drain structures can lead to abnormal growth and merging of source/drain structures, affecting device performance and reliability.
Innovation Solution
The semiconductor device incorporates a fin structure with a gate spacer and source/drain structure design where the topmost portion of the gate spacer is lower than the top surface of the fin structure, and the source/drain structure is positioned such that its top surface is lower than the fin structure, with specific doping and layer compositions to prevent abnormal growth and merging, enhancing the device's performance by increasing charge carrier mobility and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source/drain structure is formed at the same level as the fin structure, then the manufacturing process is simpler, but the source/drain structure may abnormally grow and merge, affecting device performance
Solution Approach 1:
The gate spacer is formed with its topmost portion positioned lower than the top surface of the fin structure before the source/drain structure is deposited. This preliminary configuration prevents the source/drain structure from abnormally growing and merging by establishing a physical barrier at a lower elevation, thus preventing performance degradation while maintaining manufacturing simplicity
Solution Approach 2:
The gate spacer structure is prepared in advance with a specific height relationship (topmost portion lower than fin structure top surface) before the source/drain structure formation. This preliminary action creates a controlled geometry that guides subsequent material deposition and prevents abnormal growth, resolving the contradiction between ease of manufacture and device reliability
2Shape
If the gate spacer topmost portion is at the same level as the fin structure top surface, then the structure is more compact, but the source/drain structure may merge abnormally
Solution Approach 1:
The gate spacer is deliberately designed with its topmost portion lower than the fin structure top surface, creating a preliminary anti-action that prevents the source/drain structure from bridging between fins. This height differential maintains structure compactness while ensuring proper separation of source/drain regions, thus preserving manufacturing precision
3Reliability
If the source/drain structure top surface is higher than the fin structure top surface, then the charge carrier mobility is improved, but the source/drain structure may abnormally grow and merge
Solution Approach 1:
The gate spacer configuration with its topmost portion lower than the fin structure top surface serves as a preliminary anti-action that constrains the source/drain structure growth. This allows the source/drain structure to achieve optimal height for charge carrier mobility while preventing abnormal lateral growth and merging, thus maintaining structural integrity
Solution Approach 2:
The gate spacer provides localized geometric control at specific regions (where it contacts the source/drain structure) while allowing the source/drain structure to achieve optimal height in other regions. This local quality approach enables both high charge carrier mobility and structural integrity by controlling growth only where necessary
Data Source
AI summary
A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.