FinFET Gate Spacer Structure for Source/Drain Isolation
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Solution Overview
Problem
In FinFET devices, the removal of dummy gates can lead to narrowed spacer dielectric regions, causing gate-to-source/drain encroachment and poor isolation, which affects device performance and reliability.
Innovation Solution
The process involves forming a dielectric layer with a dummy gate structure, etching a portion to create a dielectric etch back region, and using spacer elements to define different height regions, followed by selective growth of strained materials and removal of the dummy gate to form a gate structure, optimizing spacer dielectric heights to improve isolation and immunity to etching solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gates are removed after forming source/drain regions, then gate structures can be formed with proper alignment, but spacer dielectric regions become narrowed causing gate-to-source/drain encroachment and poor isolation
Solution Approach 1:
The patent applies preliminary action by forming the gate structure before removing the dummy gates. Specifically, the gate electrode and gate dielectric are formed while the dummy gates are still in place, ensuring proper alignment. The dummy gates are then removed after the gate structure is established, preventing encroachment issues. This sequence resolves the contradiction by performing the alignment-critical step first when dummy gates provide structural support.
Solution Approach 2:
The patent segments the gate formation process into distinct phases: (1) forming gate electrode and gate dielectric with dummy gates present, (2) removing dummy gates, and (3) forming source/drain regions. This segmentation allows each step to be optimized independently, maintaining alignment precision while avoiding isolation problems.
2Productivity
If spacer dielectric height is reduced to improve device density, then more devices can be packed, but susceptibility to etching solutions increases and isolation deteriorates
Solution Approach 1:
The patent changes the parameter of spacer dielectric height to different values in different regions. Specifically, first spacer dielectric regions have a first height and second spacer dielectric regions have a second height that is less than the first height. This parameter variation allows dense device packing in regions with shorter spacers while maintaining robust isolation in regions with taller spacers that are more susceptible to etching.
Solution Approach 2:
The patent applies local quality by making spacer dielectric height location-dependent. First spacer dielectric regions adjacent to certain structures maintain greater height for enhanced protection, while second spacer dielectric regions in other locations have reduced height to maximize device density. This localized differentiation optimizes both density and etching resistance where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate-to-source/drain isolation, improves device reliability, and reduces susceptibility to etching solutions, thereby improving the performance and longevity of FinFET devices.
Implementation Method 1
A strained material is selectively grown over the first recessed portion of the substrate to form a first strained recessed region
Data Source
AI summary
A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.