FinFET Gate Spacer Structure With Low-k Layers for Precise Etching
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Solution Overview
Problem
Current semiconductor devices, such as FinFETs, face challenges in reducing parasitic capacitance and achieving precise etching and epitaxial growth due to the complexity of dielectric layer structures and etch resistance properties, which affect transistor performance and size reduction.
Innovation Solution
The method involves forming a sequence of dielectric layers with varying etch resistance properties, including a low-k dielectric layer to reduce parasitic capacitance and a dielectric cap to protect these layers during etching, followed by epitaxial growth on thinned source/drain regions to enhance carrier mobility and maintain strain in channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a low-k dielectric layer is used to reduce parasitic capacitance, then parasitic capacitance is reduced, but etching precision deteriorates due to differential etching between low-k and surrounding dielectric layers
Solution Approach 1:
A mandrel structure is formed beforehand to define the precise location where the low-k dielectric layer should be removed. This preliminary structure guides the subsequent selective removal process, ensuring that only the low-k layer is removed while preserving the etching precision of surrounding layers.
Solution Approach 2:
The patent applies different dielectric materials with different etch resistance properties to different locations. The low-k dielectric layer is placed only in specific regions where parasitic capacitance reduction is needed, while other regions use dielectric layers with higher etch resistance to maintain etching precision during fabrication.
2Object-generated harmful factors
If multiple dielectric layers with varying etch resistance are formed, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The low-k dielectric layer is extracted or removed from regions where it would cause etching problems. By selectively removing the low-k layer in certain areas while maintaining it in others, the patent reduces parasitic capacitance without requiring complex multi-layer structures throughout the entire device.
Solution Approach 2:
The dielectric structure is segmented into different regions with different properties. The low-k dielectric layer is segmented to be present only in specific locations rather than as a continuous layer, simplifying the overall structure while still achieving parasitic capacitance reduction where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, improves etching precision, and enhances transistor performance by maintaining strain in channel regions, leading to improved carrier mobility and device performance.
Implementation Method 1
a second dielectric layer having a lower dielectric constant than dielectric constants of the first and third dielectric layers
Implementation Method 2
a first dielectric layer, a second dielectric layer, and a third dielectric layer lining sidewalls of the first and second gate stacks and a top surface of the fin, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers
Implementation Method 3
epitaxial growth on thinned source/drain regions to enhance carrier mobility
Data Source
AI summary
A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.