FinFET Gate Spacer Formation Using Planarizing Layer
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Solution Overview
Problem
The formation of gate spacers on FinFETs is challenging due to difficulties in completely removing spacer material from the fin while maintaining it on the gate, leading to material residue and damage during conventional etching processes.
Innovation Solution
A method involving the formation of a planarizing layer to the height of the gate fins, followed by depositing a conformal layer and etching it back to create uniform spacer heights, allowing for the use of conventional etching techniques to form spacers without damaging them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching techniques are used to form gate spacers on FinFETs, then the etching process can be simplified, but spacer material cannot be completely removed from the fin while remaining on the gate, leading to material residue and damage
Solution Approach 1:
A planarizing layer is deposited over the gate and fin structure before forming the conformal spacer layer. This preliminary action creates a uniform baseline surface that enables subsequent etching to remove material evenly from the fin while preserving the spacer material on the gate, solving the selectivity problem without requiring complex etching techniques
2Productivity
If the gate length is scaled below 100 nm to increase device density, then high density integration is achieved, but short channel effects such as excessive leakage between source and drain become increasingly difficult to overcome
Solution Approach 1:
The invention transitions from a planar MOSFET structure to a three-dimensional FinFET structure with vertical fins. This dimensional change provides better electrostatic control over the channel, effectively suppressing short channel effects and leakage currents while enabling continued scaling for high density integration
3Manufacturing precision
If a conformal layer is deposited over the gate and fins and etched back to form spacers, then spacers are formed, but material remains in the lower area and the spacers are damaged
Solution Approach 1:
The planarizing layer serves as an intermediary between the substrate and the conformal spacer layer. It provides a uniform surface that enables selective removal of material from the fin region while protecting the spacer material on the gate during the etching process, eliminating both material residue and spacer damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the successful formation of gate spacers on FinFETs using conventional etching techniques, ensuring uniformity and preventing damage to the spacers, thus addressing the challenges of spacer formation in FinFET fabrication.
Implementation Method 1
removing the planarizing layer by etching
Implementation Method 2
depositing the conformal layer by chemical vapor deposition
Implementation Method 3
etching the conformal layer
Implementation Method 4
planarizing by chemical mechanical polishing (CMP), and then etching back
Data Source
AI summary
Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.