FinFET Gate Spacer Profile for Seam-Free Replacement Gates
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration of more components into a smaller area leads to challenges such as the formation of seams or voids during the replacement gate process in FinFET manufacturing, which can affect the work function and internal gate resistance of the gate electrodes.
Innovation Solution
The process involves forming funnel-shaped gate electrodes by widening the recesses in the replacement gate process through selective impurity implantation in the gate spacers, followed by etching to remove the impurity-modified regions, which helps avoid the formation of seams when filling the gates, thereby improving the work function and reducing internal gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional replacement gate process is used, then manufacturing simplicity is maintained, but seams or voids form during gate filling affecting work function and gate resistance
Solution Approach 1:
The patent applies preliminary action by performing impurity implantation in the gate spacer regions before the gate electrode deposition step. This pre-modification of the gate spacer creates a funnel-shaped recess that facilitates complete gap filling during subsequent gate electrode deposition, preventing seam or void formation. The impurity implantation is performed at a first processing step, and the gate electrode filling occurs at a second processing step, ensuring the recess is already optimized for filling before the actual gate formation.
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but seam formation and gate filling problems worsen
Solution Approach 1:
The patent applies local quality by selectively modifying only the gate spacer regions adjacent to the fin structures through targeted impurity implantation. This creates localized funnel-shaped recesses with different properties (wider opening at top, narrower at bottom) compared to the rest of the structure. The impurity concentration and distribution are specifically tailored for the gate spacer regions, creating optimal conditions for gap filling in these critical areas while maintaining the overall device geometry and enabling higher integration density.
3Reliability
If gate spacer regions are not modified, then process simplicity is maintained, but pinch-off effects occur during gate filling
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the gate spacer regions through impurity implantation. The impurity concentration, energy, and distribution parameters are specifically adjusted to create the desired funnel-shaped recess profile. This parameter modification changes the etch rate or deposition characteristics of the gate spacer regions, enabling complete gap filling and preventing pinch-off effects during gate electrode deposition, thereby improving gate filling reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and yield of FinFETs by preventing pinch-off effects and ensuring better gap filling during gate electrode deposition, leading to improved electrical characteristics.
Implementation Method 1
implanting an impurity in the first region of the gate spacer to increase an etch rate of the first region of the gate spacer
Data Source
AI summary
In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.