FinFET Gate Spacer Segmentation for Integration Density
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Solution Overview
Problem
The down-scaling of semiconductor devices leads to a short channel effect, reducing the reliability of semiconductor devices and making precise adjustments in the fabrication process difficult, especially as design rules are reduced, resulting in variations in electrical characteristics and precision issues during the formation of active contacts.
Innovation Solution
The semiconductor device design includes a fin active region with a gate electrode, gate spacer structure, insulating capping layer, and self-aligned contact, where the gate spacer structure and insulating liner are formed with specific thicknesses and configurations to reduce the aspect ratio of the sacrificial gate stack, enhancing process precision and reducing parasitic capacitance, and the native oxide layer is used to facilitate the formation of a T-shaped insulating capping layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor device is down-scaled to increase integration, then the integration density is improved, but the short channel effect increases and reliability deteriorates
Solution Approach 1:
The gate structure is segmented into a gate electrode and a gate spacer structure with different heights. The gate spacer structure extends higher than the gate electrode, creating a stepped configuration that segments the gate region to better control the channel and reduce short channel effects while maintaining high integration density
Solution Approach 2:
The gate spacer structure is formed to extend in the vertical dimension beyond the gate electrode height. This dimensional extension creates a three-dimensional gate structure that provides better electrostatic control over the channel, reducing short channel effects without increasing the lateral footprint of the device
2Productivity
If the design rules are reduced to increase integration, then the device size is reduced, but the manufacturing precision becomes difficult to maintain
Solution Approach 1:
The gate spacer structure serves as a self-aligned mask for forming the source/drain regions. The spacer structure's position and dimensions automatically define the contact alignment, eliminating the need for separate alignment steps and maintaining precision even as design rules are reduced
Solution Approach 2:
The gate spacer structure is formed beforehand to establish the alignment reference for subsequent contact formation. This preliminary structure prepares the fabrication sequence by pre-defining the contact positions, thereby maintaining manufacturing precision through self-alignment rather than relying on precise lithographic alignment at each step
3Manufacturing precision
If the gate spacer structure and insulating liner are formed with specific thicknesses, then the aspect ratio is reduced and process precision is improved, but the device complexity increases
Solution Approach 1:
Specific thickness parameters are established for the gate spacer structure and insulating liner to achieve an optimized aspect ratio. By carefully controlling these dimensional parameters, the structure maintains good etch selectivity and process precision while the multi-layer configuration provides the necessary functional differentiation
Data Source
AI summary
A semiconductor device includes a fin active region protruding from a substrate and extending in a first direction, a gate electrode covering an upper surface and sidewalls of the fin active region and extending in a second direction crossing the first direction, a gate spacer structure on opposite sidewalls of the gate electrode, an insulating capping layer on the gate electrode and extending in the second direction, an insulating liner on opposite sidewalls of the gate electrode and on an upper surface of the gate spacer structure, and a self-aligned contact at a side of the gate electrode. The insulating liner may have a second thickness greater than a first thickness of the gate spacer structure. A sidewall of the self-aligned contact may be in contact with the gate spacer structure and the insulating liner.