FinFET Gate Spacer Thickness Variation for Hot Carrier Reliability
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Solution Overview
Problem
In the semiconductor industry, achieving uniform etch depth and controlling etch uniformity across regions with different pattern densities is challenging due to the loading effect, which affects the fabrication of integrated circuits (ICs) with FinFET devices, leading to potential defects and reduced yield.
Innovation Solution
The method involves forming semiconductor fins and gate structures with varying spacer thicknesses, where thicker spacers are used in high-voltage and I/O regions to enhance hot carrier injection reliability, while maintaining compatibility with existing FinFET processes and minimizing impact on SRAM yield and intellectual property core performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform etch depth is pursued across all regions, then manufacturing precision is improved, but device performance in high-voltage and I/O regions deteriorates due to insufficient hot carrier injection reliability
Solution Approach 1:
The patent applies different spacer thicknesses to different regions of the semiconductor device. Specifically, thicker spacers are formed in high-voltage and I/O regions to enhance hot carrier injection reliability, while thinner spacers are used in other regions to maintain etch depth uniformity. This local differentiation resolves the contradiction by allowing each region to have the specific spacer thickness optimized for its functional requirements.
2Reliability
If spacer thickness is increased to enhance hot carrier injection reliability, then device performance is improved, but etch uniformity across different pattern densities deteriorates due to the loading effect
Solution Approach 1:
The patent implements region-specific spacer thicknesses to overcome the loading effect. By forming thicker spacers only in high-voltage and I/O regions where hot carrier injection is critical, and maintaining thinner spacers in other regions, the patent achieves both improved hot carrier injection reliability and maintained etch uniformity across different pattern densities.
3Reliability
If selective adjustment of spacer thickness is made for high-voltage and I/O regions, then hot carrier injection reliability is improved, but process complexity increases
Solution Approach 1:
The patent segments the semiconductor device into different regions (high-voltage regions, I/O regions, and other regions) and applies different spacer thicknesses to each segment. This segmentation allows selective adjustment of spacer thickness in specific regions without affecting the entire device, thereby improving hot carrier injection reliability while managing process complexity through targeted modifications.
4Reliability
If thicker spacers are used in high-voltage and I/O regions, then hot carrier injection reliability is improved, but impact on SRAM yield and IP core performance may occur
Solution Approach 1:
The patent carefully localizes the thicker spacer application only to high-voltage and I/O regions where hot carrier injection is critical. By maintaining thinner spacers in SRAM and IP core regions, the patent improves hot carrier injection reliability while minimizing negative impacts on SRAM yield and IP core performance, thus resolving the contradiction between reliability improvement and productivity maintenance.
Data Source
AI summary
A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.