FinFET Memory Gate Spacer Thinning for Lower Operating Voltage
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology process nodes, challenges arise in fabricating memory devices with FinFETs, particularly in maintaining low power consumption and reducing device variations and leakage, which are exacerbated by the need for lower supply voltages, leading to issues like write failure, read disturb failure, and retention failure.
Innovation Solution
An etching process is employed to reduce the thickness of gate spacers in NMOS devices over P-well regions, creating a wider deposition window for metal gate structures, thereby increasing the volume of the metal gate and lowering the minimum operating voltage, while also forming gate structures with varying thicknesses in N-well and P-well regions to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of gate spacers is reduced in NMOS devices over P-well regions, then the minimum operating voltage is lowered and device performance is enhanced, but the manufacturing process complexity increases due to selective etching requirements
Solution Approach 1:
The patent applies local quality by selectively thinning gate spacers only in specific regions (over P-well regions in NMOS devices) while maintaining original thickness in other regions (over N-well regions). This is achieved through selective etching processes that target specific well regions, creating non-uniform gate spacer thickness profiles optimized for local device performance requirements.
Solution Approach 2:
The patent segments the gate spacer structure into different thickness zones corresponding to different well regions (P-well and N-well). By dividing the gate spacer into segments with different thicknesses, the patent enables independent optimization of device characteristics in different regions, allowing lower operating voltage in NMOS regions while maintaining standard characteristics in PMOS regions.
2Use of energy by moving object
If the supply voltage is reduced to achieve lower power consumption, then power efficiency is improved, but device variations and leakage increase leading to write failure, read disturb failure, and retention failure
Solution Approach 1:
The patent changes the physical parameter of gate spacer thickness to optimize device performance at lower supply voltages. By reducing gate spacer thickness in specific regions, the patent modifies the electric field distribution and threshold voltage characteristics, enabling devices to operate reliably at lower voltages with reduced power consumption while maintaining acceptable leakage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the minimum operating voltage of NMOS devices by over 25% and enhances device performance, addressing the challenges of low power consumption and reduced leakage, thereby stabilizing memory device operations at lower supply voltages.
Implementation Method 1
An etching process is employed to reduce the thickness of gate spacers in NMOS devices over P-well regions
Data Source
AI summary
A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.