FinFET Gate Spacer Void Structure for Short-Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher performance, higher device density, and lower costs in the fabrication and design of FinFETs and other MOSFETs, particularly in managing the dimensions and gate structures of these devices.
Innovation Solution
A method for manufacturing a semiconductor structure involving the formation of fins, dummy gate structures, and replacement with gate structures, along with the use of high-k metal gates and air gaps created by selectively removing portions of gate spacers to enhance current flow and reduce short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of FinFETs are reduced to achieve higher device density, then device density increases, but short-channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and device density while maintaining better gate control over the channel, thereby reducing short-channel effects despite miniaturization
Solution Approach 2:
The channel region is segmented into multiple vertical fins rather than a single planar channel. This segmentation increases the total channel width and current-carrying capacity while improving gate control, allowing higher device density without suffering from degraded short-channel characteristics
2Ease of manufacture
If traditional gate structures are used in miniaturized devices, then manufacturing is simpler, but current flow and performance are insufficient
Solution Approach 1:
The gate structure employs a composite high-k metal gate consisting of a high-k dielectric material layer combined with a metal gate electrode. This composite structure provides superior electrical performance and higher current flow compared to traditional silicon oxide gates, while being integrated into the existing FinFET manufacturing process
Solution Approach 2:
The gate dielectric is changed from traditional silicon oxide to high-k dielectric materials with higher permittivity values. This parameter change enables thinner effective oxide equivalents with better electrical control and higher current flow, improving device performance without requiring proportionally smaller dimensions
3Productivity
If high-k metal gate processes are applied to FinFETs to improve performance, then current flow increases, but manufacturing complexity increases
Solution Approach 1:
The high-k dielectric material is deposited conformally on the fin structures before gate patterning, and the metal gate is formed in a subsequent step. This preliminary formation of the high-k layer simplifies the overall process by establishing the gate dielectric foundation early, reducing the complexity of integrating high-k metal gate into the FinFET manufacturing sequence
Data Source
AI summary
A device includes a gate structure, a gate spacer, a contact etch stop layer (CESL), and a void region. The gate structure includes a gate dielectric layer. The gate spacer includes a first spacer layer interfacing the gate dielectric layer, and a second spacer layer spaced apart from the gate dielectric layer by the first spacer layer, and a third spacer layer over the second spacer layer. The CESL interfaces the second spacer layer and the third spacer layer of the gate spacer. The void region is between the first spacer layer and the third spacer layer. In a cross-sectional view, the second spacer layer has an inner sidewall facing the void region, the third spacer layer has an inner sidewall facing the void region, and the inner sidewall of the second spacer layer is laterally offset from the inner sidewall of the third spacer layer.