FinFET Gate Spacer Void for Leakage Reduction
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the increasing capacitance between gate electrodes and source/drain regions due to the high permittivity of dielectric materials leads to significant current leakage, which affects the performance and integration density of FinFETs.
Innovation Solution
The formation of voids between gate electrodes and source/drain regions by removing a gate spacer, which can be filled with air or vacuum, reduces the relative permittivity and thereby decreases the capacitance, enhancing the performance of FinFETs by minimizing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric materials with high permittivity are used to fill the space between gate electrodes and source/drain regions, then the insulation capability is improved, but the capacitance increases leading to current leakage
Solution Approach 1:
The patent removes the dielectric material from the space between gate electrodes and source/drain regions, creating a void structure. This extraction eliminates the harmful capacitance effect while maintaining the beneficial insulation capability, directly resolving the contradiction between insulation and current leakage.
Solution Approach 2:
The voids created by removing dielectric material are filled with inert materials such as air or vacuum. These inert environments provide electrical insulation without the parasitic capacitance effects of conventional dielectric materials, thereby reducing current leakage while maintaining insulation.
2Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but current leakage increases due to higher capacitance
Solution Approach 1:
By extracting dielectric material to form voids between gate electrodes and source/drain regions, the patent eliminates the capacitance that causes current leakage. This allows continued scaling to smaller feature sizes without the penalty of increased leakage, thereby maintaining high integration density.
Solution Approach 2:
The patent changes the permittivity parameter of the material filling the space between gate and source/drain from high (conventional dielectric) to low (air/vacuum). This parameter change reduces capacitance and current leakage, enabling further miniaturization while maintaining device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduction in capacitance between the gate electrodes and source/drain regions improves the performance of FinFETs by reducing current leakage, allowing for higher integration density and better device performance at smaller sizes.
Implementation Method 1
reduces the relative permittivity and thereby decreases the capacitance
Data Source
AI summary
A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.