Low-k FinFET Gate Spacers for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices, such as FinFETs, face challenges in reducing parasitic capacitance and achieving precise etching and epitaxial growth due to the complexity of dielectric layer interactions and etch resistance properties, which affect transistor performance and size reduction.
Innovation Solution
The method involves forming a sequence of dielectric layers with varying etch properties, including a low-k dielectric layer to reduce parasitic capacitance and a dielectric cap to protect these layers during etching, allowing for the formation of gate spacers and epitaxial source/drain structures that maintain strain and enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a low-k dielectric layer is used to reduce parasitic capacitance, then parasitic capacitance is reduced, but etching complexity increases due to varying etch resistance properties of multiple dielectric layers
Solution Approach 1:
The patent divides the dielectric structure into multiple distinct layers (first dielectric layer, low-k dielectric layer, second dielectric layer) with different etch resistance properties. Each layer is selectively etched using tailored etching conditions, allowing precise formation of gate spacers while managing the complexity through systematic segmentation of the etching process.
Solution Approach 2:
The patent applies different dielectric materials with specific etch resistance properties to different regions and layers. The low-k dielectric layer is positioned specifically where parasitic capacitance reduction is needed, while other dielectric layers provide protective functions. Each layer's etching is controlled with localized parameters to achieve precise spatial differentiation in the final structure.
2Manufacturing precision
If multiple dielectric layers with varying etch properties are formed, then gate spacer precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary conformal deposition of multiple dielectric layers with predetermined thicknesses and etch resistance properties before the actual gate spacer formation. This preliminary structuring establishes a controlled foundation that guides subsequent etching steps, ensuring precise gate spacer dimensions are achieved through pre-planned layer configurations rather than complex real-time adjustments.
Solution Approach 2:
The patent systematically varies key parameters including dielectric material composition, layer thickness, and etching conditions across different steps. By changing these parameters in a controlled sequence, the process achieves precise gate spacer formation while managing manufacturing complexity through parameter optimization rather than process complexity.
3Length of moving object
If dielectric layers are etched to form gate spacers, then transistor size reduction is achieved, but strain maintenance in channel regions becomes difficult
Solution Approach 1:
The patent introduces epitaxial source/drain structures as intermediary elements that form between the gate spacers and channel region. These epitaxial structures serve as mediators that maintain mechanical strain in the channel while accommodating the size-reduced transistor geometry. The strain is preserved through the epitaxial growth process, which can be controlled to maintain lattice matching and strain characteristics despite the smaller overall device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, protects dielectric layers during etching, and enhances transistor performance by maintaining strain in channel regions, thereby improving carrier mobility and device efficiency.
Implementation Method 1
a second dielectric layer having a lower dielectric constant than dielectric constants of the first and third dielectric layers
Implementation Method 2
etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack
Implementation Method 3
forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin
Data Source
AI summary
A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.