FinFET Gate Electrode Spacing for Short Channel Effect Suppression
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving enhanced integration, reliability, and performance, particularly in scaling techniques for multi-gate transistors, where the short channel effect (SCE) and current control capabilities are not adequately addressed.
Innovation Solution
The semiconductor device incorporates a substrate with fin patterns and isolation layers, along with gate electrodes that cross and separate these fin patterns, optimizing the fin trench widths and gate electrode spacings to improve channel control and reduce SCE, while using high dielectric constant insulating layers for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor scaling is performed, then density increases, but short channel effect becomes more severe
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-gate FinFET structures. The FinFET configuration creates vertical channels with gates wrapping around the fin structures, providing enhanced gate control over the channel in the third dimension. This dimensional change allows continued scaling and density improvement while maintaining effective SCE suppression through the wrap-around gate geometry.
Solution Approach 2:
The patent divides the channel region into multiple independent fin structures (first fin pattern, second fin pattern, third fin pattern, fourth fin pattern) separated by trenches. Each fin acts as an independent vertical channel, allowing the gate to control multiple discrete channels simultaneously. This segmentation enables higher density while each individual fin maintains good gate control to suppress SCE.
2Reliability
If gate length is increased to improve current control, then current control capability improves, but device area increases
Solution Approach 1:
The patent moves from lateral gate control in 2D planar devices to vertical wrap-around gate control in 3D FinFET structures. The gate extends along the length of the fin and wraps around it, providing control from multiple directions (top and sidewalls). This three-dimensional gate configuration achieves superior current control without requiring increased gate length, thereby avoiding area expansion.
Solution Approach 2:
The patent employs high dielectric constant insulating materials (such as HfO2, HfSiOx, or HfAlOx) in the gate dielectric layer. These high-k materials enable thinner effective oxide equivalents while maintaining or improving gate control capability. This allows compact gate structures with excellent current control without increasing device area.
3Productivity
If fin trench width is reduced to increase integration, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication techniques where the fin patterns and gate structures are formed through sequential self-aligned processes. The gate electrodes are positioned automatically relative to the fin structures without requiring additional alignment steps, and the trench isolation structures are formed self-aligned to the fin patterns. This self-alignment mechanism enables reduced trench widths and higher integration density while maintaining manufacturing precision through process-driven alignment rather than lithographic alignment.
Data Source
AI summary
A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.