FinFET Gate Stack Formation Using Dummy Placeholder
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Solution Overview
Problem
In FinFET device fabrication, the existing methods result in a gate stack being formed over a relatively thicker portion of the local trench isolation (LTI) region, leading to increased short channel effects due to the reduction in LTI thickness below the source and drain regions, which is undesirable.
Innovation Solution
A method involving patterning a fin on a semiconductor substrate, depositing a local trench isolation layer, forming a dummy gate stack, and epitaxially growing semiconductor material to define active regions, while using a capping layer to protect the LTI layer during etching, ensuring the gate stack is formed below the active regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate stack is formed over a thicker portion of the LTI region, then the manufacturing process is simplified, but short channel effects increase due to reduced LTI thickness below source and drain regions
Solution Approach 1:
A dummy gate stack is formed beforehand to serve as a placeholder structure. This preliminary structure allows the LTI layer to be deposited and patterned around it, ensuring proper thickness distribution below source and drain regions before the actual gate stack is formed in its place.
Solution Approach 2:
The dummy gate stack acts as an intermediary structure that facilitates the formation process. It temporarily occupies the gate region, enabling subsequent processing steps (LTI deposition, patterning, epitaxial growth) to proceed with correct geometry, and is later replaced by the functional gate stack.
2Length of moving object
If the LTI thickness is reduced below source and drain regions, then device scaling is improved, but short channel effects increase
Solution Approach 1:
The LTI layer is deposited and patterned to have different thicknesses at different locations: thinner below source and drain regions for scaling, and thicker in other areas to maintain proper isolation and prevent short channel effects. The dummy gate stack enables this non-uniform thickness profile.
3Device complexity
If the gate stack is formed directly without dummy structure, then process complexity is reduced, but positioning precision of gate stack relative to active regions deteriorates
Solution Approach 1:
The dummy gate stack is a simplified copy or placeholder of the final gate stack structure. It replicates the essential geometry and position requirements, allowing subsequent processing to be performed with proper alignment, and is later replaced by the functional gate stack with identical positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a FinFET device with source and drain regions having bottom surfaces above the gate stack, reducing short channel effects and enhancing device performance and yield.
Implementation Method 1
epitaxially growing a semiconductor material from exposed portions of the fin to define active regions
Implementation Method 2
performing an etching process to remove oxide material from exposed portions of the fin
Data Source
AI summary
A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (LTI) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the LTI layer, depositing a first capping layer over exposed portions of the LTI layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.